Cache replacement system and method based on instruction stream and memory access mode learning

Abstract

The invention provides a cache replacement system based on instruction stream and memory access mode learning, and the system comprises a branch prediction module for predicting the instruction stream and writing the instruction stream into an instruction fetch address queue; a memory access instruction recording module which is used for recording information of the submitted memory access instructions in sequence and writing the information into a memory access instruction buffer of the memory access instruction recording module, and querying to obtain a memory access instruction sequence; a memory access mode learning module which records the memory access instruction sequence in a memory access historical buffer, learns a memory access mode according to the memory access instruction sequence, predicts a memory access physical address of the memory access instruction and writes the memory access physical address into a memory access address queue; and a cache replacement decision module which is used for receiving the physical address of the cache replacement candidate item, searching the fetch address queue or the access address queue by using the physical address, and selecting one cache replacement candidate item as a kick-out item according to the obtained reuse distance and feeding back the kick-out item to the first-level cache. The invention further provides a corresponding method. According to the cache replacement system, the interference of out-of-order execution and cache prefetching can be avoided, and the accuracy of memory access sequence prediction is improved.

Description

technical field [0001] The invention relates to the technical field of computer architecture, in particular to a cache replacement system and method based on instruction stream and memory access pattern learning. Background technique [0002] Cache is an important mechanism in modern processors. Commonly used data is copied from the memory to the cache, and subsequent data access can be directly read from the cache, thereby reducing the number of accesses to slow DRAM memory and improving processor performance. The capacity of the cache is limited, and the replacement of the cache content in actual use is inevitable, and the performance of the cache is greatly affected by the cache replacement strategy. [0003] The cache access behavior is complex, and the memory access sequence received by the cache system in the processor will be disturbed by the out-of-order execution of the processor and the cache prefetch mechanism, which further increases the difficulty of predicting ...

AI Technical Summary

Problems solved by technology

It is difficult to learn the memory access behavior pattern based on such a complex and changeable memory access sequence, and it is necessary to face great uncertainty

[0005] None of the existing cache replacement methods can effectively reduce these uncertainties

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