High-precision phase adjustment and measurement system and method based on phase interpolation

Abstract

The invention relates to a high-precision phase adjustment and measurement system and method, in particular to a high-precision phase adjustment and measurement system and method based on phase interpolation. The high-precision phase adjustment and measurement systemincludes: a sampling clock generation module which is used for generating a sampling clock fs based on a phase adjustment module of a high-speed transceiver in the Silinus FPGA; a phase counter which is controlled by the generated sampling clock fs, wherein the value of the counter represents a phase value; and a measured channel is used for measuring the phase of a measured clock. According to the invention, the phase interpolation module in a high-speed transceiver in the Silinus FPGA is adopted, the phase of an output clock is adjusted at a constant speed and high resolution, and a new clock with small shake is equivalently generated. Compared with an on-chip common phase-locked loop PLL, the clock jitter is about 5 times smaller. The resolution of the measurement system can be close to 1 picosecond, and the phase measurement precision can be less than 500 femtoseconds.

Description

technical field [0001] The invention relates to a high-precision phase adjustment and measurement system and method, in particular to a high-precision phase adjustment and measurement system and method based on phase interpolation. Background technique [0002] As the scale of large-scale scientific experiments increases, accurate time information is more and more important for the later analysis of experimental data. The acquisition of time information depends on a high-precision clock distribution system, and the precise measurement of clock phase is the core technology of the clock distribution system. [0003] The existing common technology is mainly based on the programmable device FPGA (Field Programmable Gate Array), and implements the phase measurement of the clock in the form of firmware. One of the methods uses the ordinary phase-locked loop (PLL) inside the FPGA or an external controllable crystal oscillator to generate a clock frequency f in approaching new clo...

AI Technical Summary

Problems solved by technology

The obvious disadvantage of this type of method is that in order to cover a large measurement range, multiple delay chains need to be cascaded, and each measurement channel requires a separate delay chain, which consumes a lot of hardware and firmware resources.

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