Implementation method of any-order FIR filter based on FPGA

Abstract

The invention discloses an implementation method of an any-order FIR (Finite Impulse Response) filter based on an FPGA (Field Programmable Gate Array). The order of the implemented FIR filter is not limited by the number of blocks. According to the method, the FIR filter is subjected to block design, and ROM memories, RAM memories and multiplying units with the corresponding number are designed. By reasonably designing the number of blocks and the depth of the memories, the addresses of all the memories are uniformly controlled. On the rising edge of each FPGA work clock, convolution of a filtering coefficient and a to-be-filtered signal is completed, and filtering operation of each sampling point can be completed in a sampling period. According to the method provided by the invention, the FIR filter is subjected to block parallel processing, each block is subjected to serial processing, the operation speed and the resource consumption are both considered, and the performance is superior to that of an IP core of electronic design software.

Description

Technical field [0001] The present invention relates to a method for implementing FPGA-based FIR filter of arbitrary order, arbitrary order FIR filter used in the FPGA. Background technique [0002] The digital filter is divided into finite impulse response (FIR) filters and infinite impulse response (IIR) filter. Since the IIR filter having a recursive computation part, so that at the same frequency response, the order of the IIR filter is typically much lower than the FIR filter, the storing means less, a small filter volume. However, recursive IIR structure such that the pole system exists, all poles must be placed inside the unit circle in the design, otherwise the system is unstable; IIR filter and a recursive structure is not conducive to the FPGA; Further, the IIR filter often non-linear phase, the signal will be distorted. [0003] FIR filters can be designed with linear phase filtering system, thus ensuring a filtered signal without causing distortion; FIR pole of the sy...

AI Technical Summary

Problems solved by technology

Although the FIR IP core is integrated in the currently commonly used FPGA electronic design software, the performance is not good when implementing high-order FIR filters.

In the existing invention, there is a technology of using block thinking to realize high-order FIR filters, but all require the order of the FIR filter to be a multiple of a certain parameter in the calculation step, which restricts the design of the FIR filter

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