Implementation method of any-order FIR filter based on FPGA

An implementation method and filter technology, applied in impedance networks, digital technology networks, electrical components, etc., can solve problems such as poor performance and constraints on FIR filter design, and achieve the effect of both computing speed and resource consumption

Pending Publication Date: 2022-02-08
BEIJING INST OF AEROSPACE CONTROL DEVICES
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Although the FIR IP core is integrated in the currently commonly used FPGA electronic design software, the performance is not good when implementing high-order FIR filters.
In the existing invention, there is a technology of using block thinking to realize high-order FIR filters, but all require the order of the FIR filter to be a multiple of a certain parameter in the calculation step, which restricts the design of the FIR filter

Method used

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  • Implementation method of any-order FIR filter based on FPGA
  • Implementation method of any-order FIR filter based on FPGA
  • Implementation method of any-order FIR filter based on FPGA

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Experimental program
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Effect test

Embodiment

[0087] like image 3 The amplitude frequency response view of a FIR band pass filter is shown in the passband frequency range of 100 Hz-5kHz, and the bilateral transition strip is 20 Hz. Since the transition zone is narrower, the low frequency cutoff frequency is low, so the number of filters is higher, and is 9,500 order. Using the above steps to implement the design filter, the FPGA's working clock is 100MHz, the signal sample rate is 50 kHz, and the design multiplier pipeline is 4, then the number of pieces of blocks of the FIR filter can be calculated:

[0088]

[0089] So M take 5. Further, the number of filter coefficients included in each block can be calculated:

[0090]

[0091] So take N 1 = N 2 = N 3 = N 4 = 1901, N 5 = 1897.

[0092] Design 5 ROM memory, the depth is 1901 (address range is 0-1900), and 5 parts of the FIR filter coefficient are stored, and the 1897-1900 address of the 5 ROM memory is filled.

[0093] Use the standard sine wave of the amplitude 1 Vp-P...

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Abstract

The invention discloses an implementation method of an any-order FIR (Finite Impulse Response) filter based on an FPGA (Field Programmable Gate Array). The order of the implemented FIR filter is not limited by the number of blocks. According to the method, the FIR filter is subjected to block design, and ROM memories, RAM memories and multiplying units with the corresponding number are designed. By reasonably designing the number of blocks and the depth of the memories, the addresses of all the memories are uniformly controlled. On the rising edge of each FPGA work clock, convolution of a filtering coefficient and a to-be-filtered signal is completed, and filtering operation of each sampling point can be completed in a sampling period. According to the method provided by the invention, the FIR filter is subjected to block parallel processing, each block is subjected to serial processing, the operation speed and the resource consumption are both considered, and the performance is superior to that of an IP core of electronic design software.

Description

Technical field [0001] The present invention relates to a method for implementing FPGA-based FIR filter of arbitrary order, arbitrary order FIR filter used in the FPGA. Background technique [0002] The digital filter is divided into finite impulse response (FIR) filters and infinite impulse response (IIR) filter. Since the IIR filter having a recursive computation part, so that at the same frequency response, the order of the IIR filter is typically much lower than the FIR filter, the storing means less, a small filter volume. However, recursive IIR structure such that the pole system exists, all poles must be placed inside the unit circle in the design, otherwise the system is unstable; IIR filter and a recursive structure is not conducive to the FPGA; Further, the IIR filter often non-linear phase, the signal will be distorted. [0003] FIR filters can be designed with linear phase filtering system, thus ensuring a filtered signal without causing distortion; FIR pole of the sy...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03H17/02
CPCH03H17/0227H03H2017/0081
Inventor 赵晨赵俊鹏姚树智郑百超张宇飞王颖
Owner BEIJING INST OF AEROSPACE CONTROL DEVICES
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