8 results about "Recursive computation" patented technology

This invention discloses a method, system, equipment, and medium for calculating pressure loss in perfluorohexanone (PFH) pipeline networks, relating to the field of computer-aided design technology. The method traverses the component tree of the pipeline network building information model using a three-dimensional geometry engine to form a set of pipeline network features; constructs a directed graph topology representing the flow direction of the pipeline network, calculates potential energy loss, converts local resistance into equivalent length, and constructs a weighted directional topology weight matrix; obtains hydraulic balance under single-phase flow conditions through iterative calculation of node simultaneous equations, and generates the corresponding static pressure distribution results of the pipeline network; recursively calculates the dryness and density changes of the gas-liquid mixture using the equation of state, introduces a two-phase flow friction multiplication factor for nonlinear compensation, outputs a three-dimensional dynamic compensation pressure field model, and performs rendering and digital judgment; this solution solves the problem of low accuracy in pressure loss calculation caused by the inability of existing technologies to accurately simulate the flash evaporation effect of PPHH, thus improving the reliability of pipeline network design.

The application discloses a large-scale data analysis method based on a DBSCAN algorithm, which comprises the following steps: step one, calculating an adjacency list through ring communication; step two, locally preliminarily determining a temporary cluster number of a core point; step three, alternately broadcasting a synchronous core point cluster number; and step four, updating a boundary point cluster number through reverse ring communication. The application can well solve the efficiency problem of the DBSCAN algorithm in large-scale data clustering analysis, ingeniously decomposes the calculation step dependence problem of the recursive calculation process of the DBSCAN algorithm, makes the algorithm applicable to a distributed execution model, makes the work load of different nodes in a cluster as balanced as possible, greatly reduces the communication amount in distributed calculation, and uses a non-blocking communication mode to make the calculation and communication overlap, reduces idle waiting time, fully utilizes the memory of a calculation node, and makes the massive data clustering analysis on the cluster become a reality.

Circuits and methods for computing an order N polynomial include V decimation stages, each stage including respective multiply-and-accumulate circuitry. The multiply-and-accumulate circuitry in each stage k, in response to an input r-term and a plurality of input z-terms 0 through (Nk−1), generates output z-terms 0 through (Nk / 2−1) and an output r-term as a square of the input r-term. Each output z-term i is a sum of input z-term (2i+1) of the input z-terms and a product of input z-term 2i and the input r-term. The multiply-and-accumulate circuitry in decimation stages k for k≤(V−1) provides the output r-term and one or more output z-terms from decimation stage k as the input r-term and one or more input z-terms to the respective multiply-and-accumulate circuitry of decimation stage k+1. A recursive stage inputs from decimation stage V, the output r-term as a recursive r-term and the output z-terms as a-terms, and generates a polynomial output value z by a recursive evaluation of the recursive r-term, the a-terms, and a modulus, p.

The application belongs to the technical field of power electronic real-time simulation, and aims at the problems of insufficient simulation accuracy of traditional pure CPU simulation, limited simulation scale of FPGA simulation, communication bottleneck and poor flexibility of "CPU+FPGA" hybrid simulation, and proposes a power electronic converter small step real-time simulation method and system. The core is to build a multi-port equivalent model based on the switching function method or the improved node method, and to equivalent the nonlinear part of the converter into a controlled source and fuse the linear passive network; adopt the "CPU unique calculation + FPGA special communication" architecture, FPGA nanosecond level acquisition PWM pulse sequence transmission to CPU, CPU through the main step nesting small step recursive calculation, in the microsecond level main step, reproduce the hundred nanosecond level electrical dynamic. The matching special system deeply optimizes the CPU multi-core parallel ability, the communication cost is low, realizes the accuracy, the efficiency and the scale unification, the cost is low, the flexibility is high, can support the large-scale high switching frequency system high precision simulation, is applicable to the new energy grid connection, direct current transmission and other scenes.

A technique uses linear prediction to determine the location of spurious content in a digital phase-locked loop and suppresses the spurious content from propagating to the clock output. In at least one embodiment, the technique implements an iterative (e.g., recursive) computation.

This invention discloses a recurrent neural network physical architecture based on artificial surface plasmon supercells, relating to the interdisciplinary fields of metamaterials, surface plasmons, and brain-like computing. The architecture consists of multiple identical planar network layers stacked sequentially in the vertical direction. Each layer includes a dielectric substrate (1), an SSPP supercell array (2), a bi-line divider (3), and a combiner (4). The SSPP supercell array is connected to inter-layer feedback links via vias. Its output is divided into an output path and a feedback path by a bi-line divider. The feedback path integrates an RF amplifier (5) for gain compensation and transmits the signal across layers to the combiner in the next layer for vector superposition with the new input signal. This architecture integrates temporal feature extraction, nonlinear modulation, and recursive computation, possessing ultra-high-speed parallel processing capabilities, and can effectively realize deep fusion and associative decision-making of multimodal information based on the nonlinear coherence effect of SSPP waves.

The application provides an iteration-based arithmetic mask and Boolean mask conversion method and system, relates to the technical field of side channel security protection, and comprises the following steps: obtaining a target arithmetic mask sequence corresponding to an original secret value, wherein the sum of all arithmetic masks in the sequence is equal to the original secret value; taking each arithmetic mask in the target arithmetic mask sequence as a leaf node to construct a complete binary tree; starting from the leftmost leaf node of the complete binary tree, recursively calculating the Boolean mask sequence of each parent node until the calculation of the Boolean mask sequence of the root node is completed; and taking the Boolean mask sequence of the root node as the Boolean mask sequence of the original secret value, wherein the XOR sum of all Boolean masks in the sequence is equal to the original secret value; the application significantly improves the conversion efficiency between the arithmetic mask and the Boolean mask under the premise of ensuring the security of the mask, so that a better balance between performance and security is achieved in the side channel security protection.

This invention discloses a method, system, terminal, and storage medium for reasoning about text information. The method includes: acquiring long text information of a target application; extracting features from the long text information to obtain a floating-point feature vector; converting the floating-point feature vector to obtain a binary sequence; performing bit mapping on the binary sequence to obtain a packaged query vector; performing logical operations on the packaged query vector to obtain a Boolean matching mask; recursively calculating the Boolean matching mask to obtain the longest common suffix length state; and performing text reasoning based on the longest common suffix length state to obtain a long text reasoning result. This invention reduces the number of main memory accesses and memory usage while improving the reasoning efficiency and accuracy of context information.