Method for preventing NiSi from generating recess in HK metal gate process

Abstract

The invention provides a method for preventing NiSi from generating recesses in an HK metal gate process. A substrate is provided with a dense region, a sparse region and an open region in which dummy gates are distributed; and the dummy gate comprises an amorphous silicon structure and a side wall thereof. The method comprises the following steps: forming a NiSi layer on the substrate; depositing an interlayer dielectric layer covering the dummy gate on the substrate, wherein the interlayer dielectric layer is composed of a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer from bottom to top in sequence; grinding the second oxide layer by adopting a selection ratio that silicon oxide and silicon nitride are greater than 1, and stopping grinding until the silicon nitride layer; and etching the silicon nitride layer and the first silicon oxide layer, and removing the amorphous silicon structure in the dummy gate. According to the method disclosed by the invention, the final height of the interlayer dielectric layer can be controlled within a range with small difference in each pattern region, so that the surface of an active region of an open region is not damaged in the process of removing the dummy grid polycrystalline silicon, and the NiSi recess defect is avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for avoiding NiSi recesses in the HK metal gate process. Background technique [0002] With the development of the times, chips have become a "necessity" for global life. With the advancement of chip technology, people's lives are becoming more and more intelligent, various travels are becoming more and more convenient, and the amount of information available every day is also increasing. Big. Today, as the requirements for integrated circuit design and manufacturing are getting higher and higher, the feature size of MOS tubes is getting smaller and smaller, and many processes are even constantly squeezing the limits of the process. [0003] One of the important links in the reduction of feature size is that the line width of the polysilicon gate (metal gate) becomes smaller, and then the distance between the gate and the gate also becomes smaller, so as to achie...

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Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a method for avoiding NiSi depressions in the HK metal gate process, which is used to solve the problems in the prior art due to the sparse and dense graphics after grinding. The problem of generating defects on NiSi

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