Storage system, storage controller and storage chip

Abstract

The invention discloses a storage system. A storage system includes a memory, a controller, and a physical layer. The memory comprises a data bus and an STB gate with a single pin, and the memory receives a parallel command by using the data bus and receives a serial command by using the STB gate. The physical layer converts STB input data sent by the controller into a serial command, and the serial command is transmitted to the memory through the STB gate.

Description

technical field [0001] The invention relates to a storage system, a storage controller and a storage chip, in particular to a storage system and a storage chip capable of parallel and serial transmission of data between the storage controller and the storage chip. Background technique [0002] Today, memory systems used in high-performance computing or artificial intelligence systems typically include dynamic random access memory chips and logic circuits. Due to the stack structure of the DRAM chip, the size of the DRAM chip cannot keep up with the size of the logic circuit. Therefore, a memory-wall effect occurs, resulting in a decrease in the data transfer rate between the logic circuit and the DRAM chip. In order to overcome the storage wall effect, the prior art usually uses a faster data rate (for example, from double data rate three (DDR3) to double data rate fourth (DDR4) or double data rate fifth (DDR5)) in the transfer data between the dynamic random access memory...

AI Technical Summary

Problems solved by technology

But as the number of signals decreases, the maximum bandwidth of the bus also decreases, for a given switching speed: only fewer switching signals are used to transmit information

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