EDA (Electronic Design Automation) hardware acceleration method and system based on Banyan network and multi-FPGA (Field Programmable Gate Array) structure

A hardware acceleration and network technology, which is applied in the direction of multi-program device, program startup/switching, resource allocation, etc., can solve the problem of occupying large resources, achieve efficient functions, realize simple structure, and reduce the effect of data exchange delay

Pending Publication Date: 2022-02-25
XIAMEN UNIV
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Problems solved by technology

The transmission efficiency of the cross-interconnection and hybrid interconnection structures is greatly improved, but it will take up a lot of resources when the number of FPGA blocks is large

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  • EDA (Electronic Design Automation) hardware acceleration method and system based on Banyan network and multi-FPGA (Field Programmable Gate Array) structure
  • EDA (Electronic Design Automation) hardware acceleration method and system based on Banyan network and multi-FPGA (Field Programmable Gate Array) structure
  • EDA (Electronic Design Automation) hardware acceleration method and system based on Banyan network and multi-FPGA (Field Programmable Gate Array) structure

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[0046] The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. It should also be noted that, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0047] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0048] A kind of EDA hardware acceleration method based on Banyan network and multi-FPGA structure according to an embodiment of the present invention, figure 1 A flowchart of an EDA hardware acceleration method based on a Banyan network and a multi-FPGA structure is shown a...

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Abstract

The invention provides an EDA (Electronic Design Automation) hardware acceleration method and system based on a Banyan network and a multi-FPGA (Field Programmable Gate Array) structure, which comprises the following steps of: combining EDA algorithm acceleration and simulation acceleration in one system, starting a top EDA algorithm to control the sending and receiving of data when EDA algorithm acceleration is carried out, and carrying out EDA simulation acceleration according to a to-be-tested design structure designed by a user and simulation data input by the user when the EDA simulation acceleration is carried out; while using a multi-channel SCE-MI interface for software and hardware data collaboration, and using a Banyan network for achieving data exchange of multiple FPGAs; and finally, returning the accelerated data for processing, comparing simulation data with verification data to verify a simulation result, or returning operation result data to external EDA software. An algorithm and simulation are accelerated in a software and hardware cooperation mode, EDA algorithm acceleration and simulation acceleration are combined, a multi-channel PIPE type SCE-MI standard protocol interface is adopted, universality is achieved, meanwhile, a Banoan network is applied to multi-FPGA data exchange, data exchange delay is reduced, and the system is simple in implementation structure and efficient in function.

Description

technical field [0001] The invention relates to the technical field of EDA hardware acceleration, in particular to an EDA hardware acceleration method and system based on a Banyan network and a multi-FPGA structure. Background technique [0002] With the continuous development of the IC design industry and the continuous progress of ultra-large-scale IC process technology, the scale and complexity of IC design have doubled, which requires the computing power of EDA software to process simulation, synthesis, layout and wiring, verification and other processes. greatly increase. The calculation process of these EDA software often occupies a large amount of design time. As a kind of computing-intensive high-speed computing device with flexible configuration, FPGA has certain advantages when dealing with large-scale data computing and circuit simulation, and the proposal of multi-FPGA system is undoubtedly the icing on the cake. [0003] In a multi-FPGA system, the implementat...

Claims

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Application Information

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IPC IPC(8): G06F9/50G06F9/48
CPCG06F9/5044G06F9/4843
Inventor 郭东辉沈云飞马钦鸿贺珊
Owner XIAMEN UNIV
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