FPGA prototype verification clock device

Abstract

The embodiment of the invention provides an FPGA (Field Programmable Gate Array) prototype verification clock device, which is used for meeting the requirements of an ASIC (Application Specific Integrated Circuit) on at least two irrelevant clock signals. The device comprises a clock generation module and a verification module, the clock generation module and the verification module are located on different PCBs, and the clock generation module comprises a first-stage frequency synthesizer and a plurality of second-stage frequency synthesizers; the first-stage frequency synthesizer is used for generating N first clock signals and outputting the N first clock signals to the N second-stage frequency synthesizers; one of the N second-stage frequency synthesizers is used for generating M second clock signals according to one of the N first clock signals and outputting the M second clock signals to the verification module; one of the plurality of second-stage frequency synthesizers except the N second-stage frequency synthesizers is used for generating H third clock signals and outputting the H third clock signals to the verification module; and the verification module is used for verifying the application-specific integrated circuit according to the fourth clock signal.

Description

technical field [0001] The present application relates to the field of field programmable gate array (field programmable gate array, FPGA) prototype verification technology, in particular to an FPGA prototype verification clock device. Background technique [0002] The FPGA prototype verification clock device can be used for functional verification and / or performance verification of the register transfer level (RTL) prototype code of an application specific integrated circuit (ASIC), so as to shorten the development cycle of the ASIC and improve the performance of the ASIC. Accuracy and Availability. The FPGA prototype verification clock device can include a circuit module and a verification module, the verification module includes at least one FPGA chip, the at least one FPGA chip is used to store the RTL prototype code of the ASIC, and the circuit module is used to generate a synchronous clock signal and output the synchronous clock signal Provide at least one FPGA chip, ...

AI Technical Summary

Problems solved by technology

[0004] On the one hand, the verification module and the circuit module in the FPGA prototype verification clock device are located on the same PCB. The two are structurally coupled, interact with each other, and have poor portability. If one of the modules fails, the other module will be unavailable, resulting in Waste of resources; on the other hand, as the ASIC design becomes more and more complex, the verification module needs to complete the verification of the RTL prototype code of the ASIC based on at least two unrelated clock signals, but a set of clock signals input into the FPGA chip Each of them is a synchronous clock signal generated according to the synchronous clock signal output by the frequency synthesizer 1-0. Any two of the clock signals in this group form a synchronous relationship and are interrelated, which cannot satisfy the requirements of the ASIC for at least two uncorrelated clock signals. The clock signal needs of the

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