FDSOI silicon epitaxial growth process optimization method

A technology of process optimization and silicon epitaxy, which is applied in the manufacture of electrical components, circuits, semiconductors/solid-state devices, etc., can solve the problems of excessive loss of top-layer silicon and the inability of epitaxial growth of top-layer silicon to achieve the goal of making up for loss and increasing thickness Effect

Active Publication Date: 2022-03-01
GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST +1
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Problems solved by technology

[0004] Aiming at the problem existing in the prior art that the top silicon of the FDSOI transistor is blocked or oxidized, cleaned and other processes tend to cause excessive loss of the top silicon, resulting in the problem that the top silicon above the active region cannot be epitaxially grown or the effect of epitaxial growth is poor. The present invention provides An F

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  • FDSOI silicon epitaxial growth process optimization method
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  • FDSOI silicon epitaxial growth process optimization method

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[0054] In order to better understand the present invention, the technical solutions in the embodiments of the present invention will be described in contemplation, and It is an embodiment of the invention, not all of the embodiments. Based on the embodiments in the present invention, those of ordinary skill in the art may belong to the scope of the present invention in the range of the present invention without all other embodiments obtained without making creative labor.

[0055] It should be noted that the terms "of the present invention" and "include" and "have" and "have any deformed", which are intended to cover the contained, such as a series of steps or units. The processes, methods, devices, products, or devices are not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or for these processes, methods, products, or equipment.

[0056] A FDSOI silicon epitaxial growth process optimization met...

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Abstract

The invention discloses an FDSOI silicon epitaxial growth process optimization method, which can ensure that top silicon above an active region can completely grow, a transistor comprises a substrate, the active region, a trench isolation region and a gate region are distributed on the substrate, the substrate is divided into a plurality of substrate regions, one trench isolation region is arranged between two adjacent substrate regions, and the gate region is arranged between the active region and the gate region. And growing epitaxial layers on the top layer silicon of different substrate regions respectively, and the process optimization step comprises the following steps of: sequentially depositing a first layer of top layer silicon on the active regions of the different substrate regions, depositing thin films on the upper surfaces of the first layer of top layer silicon, the gate region and the trench isolation region, arranging a mask plate on the thin films, and forming a second layer of top layer silicon on the active regions of the different substrate regions. And etching the mask above the corresponding substrate area, etching the thin film above the corresponding substrate area, further cleaning by adopting a pre-cleaning technology, drying the first layer of top silicon, depositing a second layer of top silicon on the surface of the first layer of top silicon, forming a combined top silicon, and enabling the combined top silicon to grow an epitaxial layer.

Description

technical field [0001] The invention relates to the technical field of transistor processing, in particular to an FDSOI silicon epitaxial growth process optimization method. Background technique [0002] Field effect transistor is a voltage-controlled semiconductor device, mainly including planar field effect transistor (MOSFET), fin field effect transistor (FinFET, released in 1999) and SOI-based ultra-thin silicon-on-insulator transistor (FDSOI, 2000 Published), when the gate length approaches 20 nanometers, the ability to control the current drops sharply, and the leakage rate increases accordingly. In the traditional planar MOSFET structure, it is no longer applicable. The FinFET structure and FDSOI structure can meet the requirements of reducing the gate length while ensuring the control capability of the gate voltage on the source and drain currents. [0003] At present, the gate length of FDSOI planar transistors can be reduced to less than 14 nanometers. A large num...

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Application Information

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IPC IPC(8): H01L21/02H01L21/84
CPCH01L21/02381H01L21/02532H01L21/02658H01L21/02661H01L21/84
Inventor 苏炳熏叶甜春朱纪军李彬鸿罗军赵杰
Owner GUANGDONG GREATER BAY AREA INST OF INTEGRATED CIRCUIT & SYST
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