Method, device and chip for communication based on serial peripheral interface

Abstract

The invention relates to a communication method, device and chip based on a serial peripheral interface. In order to solve the problem of complex wiring of the existing serial peripheral interface, the present invention configures multiple slaves in one address space, and all slaves share the clock and MOSI signal output by the master; all slaves perform identification checks in parallel to determine their It is a target slave or a non-target slave. The target slave responds to the host MOSI signal and resets the output of the non-target slave. The outputs of all slaves are logically operated to generate the MISO signal received by the host. The invention determines the target slave by identifying and checking rather than the chip selection signal line, and the generation of the master MISO signal is realized by simple logic gates, the structure is lighter and more flexible, and the problem of complicated routing and multiple target slaves can be solved problem, and the chip select signal can have or not, and realize the technical effect of low cost, low delay and high reliability, and is suitable for the field of brain-like chips.

Description

technical field [0001] The invention relates to a communication data interface, in particular to the field of brain-like chips, and has a method, a device and a chip for communicating with serial peripheral interfaces of a single master and multiple slaves. Background technique [0002] Serial Peripheral Interface (SPI) is a synchronous serial communication interface. There is no gap in synchronous transmission. When there is no information to be transmitted, empty characters must be filled in for transmission. The transmission and reception of data in SPI use different lines, which is a full-duplex bus. At the same time, SPI can be configured as a full-duplex working mode and a half-duplex working mode according to needs. SPI has many advantages, such as simple software configuration, simple hardware implementation (shift register), flexible data transmission, etc. [0003] A classic SPI structure with multiple slaves such as figure 1 As shown, it includes a master master...

AI Technical Summary

Problems solved by technology

However, due to the sequential transmission from one device to the next in a serial manner, there is a delay, and if a device in the data link fails, the lower priority devices below it cannot be served. up

In order to avoid the situation where a single machine is damaged and the entire link collapses, some schemes short-circuit the overtimed slave, but this increases the complexity

In some other daisy chain SPI extension schemes, each slave has 8 pins, and the signal lines between the slaves are connected in series, but adding pins is fatal for SPI

In addition, there are some schemes to judge according to the device address. However, in this scheme, each slave occupies an address space, which wastes storage resources and is not flexible enough.

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