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Wafer bonding structure and wafer bonding method

A wafer bonding and wafer technology, applied in electrical components, electric solid state devices, circuits, etc., can solve the problems of edge chipping, wafer edge hidden cracks, splits, etc., to reduce edge chipping, reduce production costs, reduce The effect of the risk of splintering

Pending Publication Date: 2022-03-25
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

When its thickness is thinned from the back side of one of the wafers, such as the back side of the first wafer 1, when it is thinned to a certain extent, such as figure 2 As shown, under the pressure and torque of the grinding wheel of the thinning machine, it will cause hidden cracks 4 on the edge of the wafer, or edge chipping or even cracks

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  • Wafer bonding structure and wafer bonding method
  • Wafer bonding structure and wafer bonding method
  • Wafer bonding structure and wafer bonding method

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Embodiment Construction

[0037] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the present disclosure will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

[0038] Such as image 3 As shown, the embodiment of the present disclosure relates to a wafer bonding structure, including a first wafer 1 and a second wafer 2 bonded to each other, the first wafer 1 is a wafer to be thinned, and the first wafer 1 is a wafer to be thinned. An edge region of a wafer 1 facing the second wafer 2 is provided with a chamfering structure 5 , and the cross section of the chamfering structure 5 is non-right-angled.

[0039] Specifically, such as image 3 As shown, a chamfering structure 5 is provided on the edge region of the lower surface of the first wafer 1 . The cross-section of the trimming structure 5 is non-rectangular, that is to say, as image 3 As shown, the trimming structure 5 ado...

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Abstract

The invention provides a wafer bonding structure and a wafer bonding method. The wafer bonding structure comprises a first wafer and a second wafer which are bonded with each other, the first wafer is a to-be-thinned wafer, the edge area of one side, facing the second wafer, of the first wafer is provided with a trimming structure, and the cross section of the trimming structure is in a non-right-angle shape. According to the wafer bonding structure disclosed by the invention, the non-right-angle-shaped trimming structure is arranged in the edge area of the wafer to be thinned, so that in the thinning process after bonding, the phenomena of edge breakage, cracks or wafer cracking and the like caused by pressure generated by thinning equipment (such as a grinding disc and the like) can be effectively reduced; therefore, the risk that the wafer is cracked in the thinning process can be effectively reduced, the manufacturing yield of the wafer is improved, and the manufacturing cost is reduced.

Description

technical field [0001] The disclosure belongs to the technical field of semiconductor packaging, and in particular relates to a wafer bonding structure and a wafer bonding method. Background technique [0002] In the field of advanced packaging technology, temporary bonding, hybrid bonding and fusion bonding techniques are commonly used. Such as figure 1 As shown, in the bonding process, two wafers are bonded together. Since the edge of the standard wafer is in a blunt arc shape, the edge of the bond between the first wafer 1 and the second wafer 2 will appear with a width of about 200um suspended part 3. When its thickness is thinned from the back side of one of the wafers, such as the back side of the first wafer 1, when it is thinned to a certain extent, such as figure 2 As shown, under the action of the pressure and torque of the grinding wheel of the thinning machine, hidden cracks 4, edge chipping or even splits will be caused on the edge of the wafer. [0003] Du...

Claims

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Application Information

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IPC IPC(8): H01L23/488H01L21/60H01L29/06
CPCH01L23/488H01L24/80H01L29/0657
Inventor 马力项敏李红雷郑子企
Owner NANTONG FUJITSU MICROELECTRONICS