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Semiconductor device and method of manufacturing the same

A manufacturing method and semiconductor technology, which are applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., can solve the problems of reduced conductive layer height, leakage characteristics, and increased word line wiring resistance.

Pending Publication Date: 2022-03-25
KIOXIA CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, as the size of the conductive layer decreases, the wiring resistance of the word line increases accordingly.
In addition, if the barrier film is thinned or omitted in order to reduce the wiring resistance, for example, reliability such as leakage characteristics will be deteriorated.

Method used

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  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same
  • Semiconductor device and method of manufacturing the same

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no. 1 Embodiment approach

[0026] figure 1 It is a diagram showing a configuration example of a memory cell array in the semiconductor memory device according to the first embodiment. The memory cell array MCA is, for example, a three-dimensional memory cell array in which memory cells are three-dimensionally arranged. In addition, in figure 1 In FIG. 10 , the illustration of the insulating portion other than the insulating film formed in the memory hole 113 is omitted for easy viewing of the drawing. In addition, silicon is exemplified as a semiconductor in the following embodiments, but semiconductors other than silicon may also be used.

[0027] In addition, in this specification, for convenience of explanation, an XYZ rectangular coordinate system is introduced. In this coordinate system, two directions parallel to the main surface of the substrate 100 and orthogonal to each other are defined as the X direction and the Y direction, and the two directions perpendicular to the X direction and the Y...

no. 2 Embodiment approach

[0080] Figure 11 It is a sectional view showing the structure of the semiconductor device of the second embodiment. The second embodiment differs from the first embodiment in that nitrogen is contained in the metal layer 211 .

[0081] The metal layer 211 also contains nitrogen (N). In more detail, the metal layer 211 contains ammonia (NH 3 )214. For example, a nitride layer having a high nitrogen concentration is formed in the metal layer 211 near the interface with the barrier insulating film 21a. Nitrogen in the metal layer 211 can improve the adhesion between the barrier insulating film 21 a and the metal layer 211 (conductive layer 21 ). This is considered to be because, for example, nitrogen in the metal layer 211 is chemically bonded to tungsten (W-N) and silicon (Si-N) in the metal layer 211 and aluminum (Al-N) in the barrier insulating film 21 a.

[0082] Figure 12 yes means Figure 11 A schematic diagram of the nitrogen concentration in the metal layer 211. ...

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Abstract

Embodiments provide a semiconductor device capable of suppressing reliability degradation and a method of manufacturing the same. According to one embodiment, a semiconductor device includes a stacked body including a plurality of conductive layers and a plurality of first insulating layers alternately stacked in a first direction. The conductive layer has a first metal layer and a second metal layer. The first metal layer contains a first metal element and a substance that chemically reacts with a material gas containing the first metal element. The second metal layer contains the first metal element, and the content of the second metal layer is less than that of the first metal layer. The first metal layer is disposed between the first insulating layer and the second insulating layer.

Description

[0001] [Cross-reference to related applications] [0002] This application enjoys the priority of the basic application based on Japanese Patent Application No. 2020-151432 (filing date: September 9, 2020). This application incorporates all the contents of the basic application by referring to this basic application. technical field [0003] This embodiment mode relates to a semiconductor device and a manufacturing method thereof. Background technique [0004] Semiconductor devices (semiconductor storage devices) such as NAND (Not AND) type EEPROM (Electrically Erasable Programmable Read-only Memory, Electrically Erasable Programmable Read-only Memory) sometimes have three-dimensional memory cells in which memory cells are arranged three-dimensionally. cell array. Such a memory cell array has a laminate in which conductive layers and insulating layers functioning as word lines are alternately laminated. [0005] However, with miniaturization, the height of the conductive ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/1157H01L27/11575H01L27/11582H01L23/532H01L21/768
CPCH01L23/53261H01L21/76838H10B43/35H10B43/50H10B43/27H01L29/40117H01L23/5226H01L21/76877H01L21/76802H01L21/76843H01L23/53266
Inventor 井手谦一田原宽子
Owner KIOXIA CORP
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