The invention provides a static memory. The static memory comprises a plurality of memory elements arranged in an array; a word line; a first
transmission line and a second
transmission line connected to the plurality of memory cells located in the same column; the
memory cell includes: a first
transistor coupled to a first node, a first power line, and a second node, respectively; a second
transistor coupled to the second node, the first power line, and the first node, respectively; a third
transistor coupled to the first node, the second node, and a second power line, respectively; a fourth transistor coupled to the second node, the first node, and a second power line, respectively; the fifth transistor is respectively coupled with the word line, the second node and the first
transmission line, and the fifth transistor is a PMOS (P-channel
Metal Oxide Semiconductor); and the sixth transistor is respectively coupled with the word line, the first node and the second transmission line, and the sixth transistor is a PMOS (P-channel
Metal Oxide Semiconductor). According to the SRAM disclosed by the invention, a read-write path is changed, and a pull-down tube can be prepared by adopting an
oxide transistor.