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Semiconductor memory device

A storage device and semiconductor technology, which is applied in semiconductor devices, information storage, semiconductor/solid-state device manufacturing, etc., can solve problems such as component reliability degradation and large electrical stress, and achieve the effect of improving characteristics and suppressing reliability degradation

Active Publication Date: 2013-11-20
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, excess drop voltage occurs on the bit line, and unnecessary large electrical stress is applied to the transistor connected to the bit line, which promotes the deterioration of reliability of the element.

Method used

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  • Semiconductor memory device
  • Semiconductor memory device
  • Semiconductor memory device

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0040] figure 1 It is a configuration diagram of the semiconductor memory device according to Embodiment 1 of the present invention. figure 1The shown semiconductor storage device is composed of a memory cell 100 with drive transistors QN11, QN12, access transistors QN13, QN14 and load transistors QP11, QP12 respectively; a precharge circuit 101 with P-type MOS transistors QP13 and QP14 respectively; Column selection circuit 102 of MOS transistors QN15 and QN16 ; clamp circuit 103A including variable capacitance element C11 and N-type MOS transistor QN17 ; and input circuit 110 are configured.

[0041] In addition, WL1-2 represent word lines, BL1-2, / BL1-2 represent bit lines, PCG represent precharge control signals, WT1-2, / WT1-2 represent write control signals, CIN represent capacitive element control signals, COUT Indicates the output node of the capacitive element, and VDD indicates the power supply.

[0042] In the memory cell 100, the load transistor QP11, the drive tr...

Embodiment approach 2

[0066] Figure 11 It is a configuration diagram of a semiconductor memory device according to Embodiment 2 of the present invention. Figure 11 The shown semiconductor storage device is composed of a memory unit 100 with drive transistors QN11, QN12, access transistors QN13, QN14, load transistors QP11, QP12 respectively; a precharge circuit 101 with P-type MOS transistors QP13 and QP14 respectively; The column selection circuit 102 of MOS transistors QN15 and QN16; and the clamp circuit 104 are constituted. Clamp circuit 104 includes booster circuit 105 including capacitive element C13 and inverter INV11, power supply voltage detector 115, N-type MOS transistors QN17 and QN18, and capacitive element C14.

[0067] In addition, WL1-2 represent word lines, BL1-2, / BL1-2 represent bit lines, PCG represent precharge control signals, WT1-2, / WT1-2 represent write control signals, CIN represent capacitive element control signals, COUT Indicates the output node of the capacitive el...

Embodiment approach 3

[0078] Figure 12 It is a configuration diagram of a semiconductor memory device according to Embodiment 3 of the present invention. Figure 12 The illustrated semiconductor storage device is configured by including a plurality of hierarchical arrays 200A, and the hierarchical array 200A includes a memory array MA21 composed of a plurality of memory cells, and a precharge circuit 201 composed of P-type MOS transistors QP21, QP22, and QP23. , a hierarchical writing circuit 202A composed of a capacitive element C21, an N-type MOS transistor QN23, and an inverter INV21, and a local bit line selection switch 203 composed of N-type MOS transistors QN21 and QN22.

[0079] In addition, LBL1 and / LBL1 represent local bit lines, GBL1 and / GBL1 represent global bit lines, PCG represents a precharge control signal, WAS1 to 2 represent write array selection signals, COUT represents a capacitive element output node, and VDD represents a power supply.

[0080] The memory array MA21 is conn...

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Abstract

A semiconductor memory device includes a memory cell provided at an intersection of a word line and a bit line, a precharge circuit connected to the bit line, a column select circuit controlled in accordance with a write control signal, and a clamp circuit provided as a write circuit. The clamp circuit includes a transistor configured to control the potential of a selected bit line to a first potential (e.g., 0 V), and a variable capacitor configured to control the potential of the selected bit line to a second potential (e.g., a negative potential) which is lower than the first potential. The capacitance of the variable capacitor decreases when a power supply voltage is increased, whereby the amount of a decrease from the first potential to the second potential is reduced.

Description

technical field [0001] The present invention relates to a semiconductor memory device such as a static random access memory (SRAM), and more particularly to a bit line voltage control technique. Background technique [0002] In recent years, the miniaturization of the semiconductor process has progressed, and the reliability (resistance to electrical stress, thermal stress, etc.) of the semiconductor element has decreased. [0003] In a method of writing data to a memory cell in a general semiconductor memory device such as SRAM, the potential of any one of the bit line pairs precharged to the H level is changed from the H level to the L level. implement. [0004] For example, Patent Document 1 discloses a technique for improving writing characteristics of memory cells with a low power supply voltage by setting the potential of a bit line to a negative potential lower than 0V when data is written into the memory cells. [0005] Patent Document 1: Japanese Patent Laid-Open ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/417G11C11/4074G11C11/41G11C11/418H01L21/8244H01L27/11H03K19/0185
CPCG11C11/413H01L27/1104H01L27/0207G11C2207/002G11C7/12H10B10/12
Inventor 蓝原智之白滨政则山上由展车田希总铃木利一
Owner SOCIONEXT INC
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