On-chip cache design method and on-chip cache based on bank compilation and layout coordination

Abstract

The present application relates to an on-chip cache design method and an on-chip cache in which storage body compilation and layout are coordinated. The method performs pre-layout planning on the glue logic, obtains its layout area, marks the layout area as a layout area, selects the convergence point of the storage body in the layout area, and uses the convergence point as the distance calculation between the storage body and the glue logic Reference point, select the position closest to the convergence point in the unlayouted area as the layout position of the current memory bank, calculate the timing requirements of the current memory bank at the layout position according to the distance between the layout position and the convergence point, and calculate the timing requirements for the current memory bank Exhaustive compilation is performed to obtain a set of candidate compilation configurations of the current memory bank, and a compilation configuration that meets timing requirements is selected from the set. By adopting the method, the location information of the memory bank can be considered while compiling the memory bank, so that the timing requirements for memory bank compilation can be accurately formulated, and the memory bank with the speed meeting the requirements and the best power consumption can be compiled.

Description

technical field [0001] The present application relates to the technical field of computer chips, in particular to an on-chip cache design method and an on-chip cache in which memory bank compilation and layout are coordinated. Background technique [0002] Modern microprocessors and various SOC chips have large-capacity on-chip caches, which are generally composed of memory banks generated by memory bank compilers. Multiple such memory banks are combined and selected by glue logic to form various large-capacity caches. On-chip cache structures such as Cache, Scratch Pad Memory, and shared buffer pool. The capacity of the on-chip cache continues to increase, and its area reaches 30% to 45% or more of the whole chip, and the proportion of power consumption also increases accordingly. At the same time, the on-chip cache is often in the critical timing path, which determines the frequency of the whole chip. Therefore, how to further improve the performance of the on-chip cache ...

AI Technical Summary

Problems solved by technology

Makes it necessary to reserve a large timing margin when compiling the memory bank, resulting in unnecessary area and power consumption overhead

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