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Level conversion circuit

A technology for converting circuits and levels, applied in the connection/interface arrangement of logic circuits, coupling/interfaces of logic circuits using field effect transistors, etc., can solve the problem that the level conversion circuit 10 cannot operate normally and affects the reliability of NMOS transistors nlvt1 and nlvt2. It can avoid problems such as resistance, drain-gate voltage difference, etc., to avoid bias voltage sources, ensure reliability, and reduce circuit area.

Pending Publication Date: 2022-04-22
SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Taking the voltage value output by the power supply voltage output terminal VDDIO as 1.8V as an example, in the above-mentioned level conversion circuit 10, the drain voltages of the NMOS transistors nlvt1 and nlvt2 will reach above the nominal voltage (0.8V), which will make the NMOS The drain-gate voltage difference or the source-drain voltage difference of the transistors nlvt1 and nlvt2 itself has an overdrive problem, which affects the reliability of the NMOS transistors nlvt1 and nlvt2, and ultimately affects the normal operation of the level conversion circuit 10

Method used

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Embodiment Construction

[0039] like figure 1 As shown, the level conversion circuit 10 includes: PMOS transistors phvt1-phvt4, and NMOS transistors nlvt1 and nlvt2. Among them, the PMOS transistors phvt1-phvt4 are high-voltage CMOS transistors, and the NMOS transistors nlvt1 and nlvt2 are low-voltage CMOS transistors.

[0040] The gate of the PMOS transistor phvt1 and the gate of the NMOS transistor nlvt1 are both connected to the first input terminal IN. The gate of the PMOS transistor phvt2 and the gate of the NMOS transistor nlvt2 are both connected to the second input terminal INb. The gate of the PMOS transistor phvt3 is connected to the drain of the PMOS transistor phvt2 and serves as the first output terminal Out. The gate of the PMOS transistor phvt4 is connected to the drain of the PMOS transistor phvt1 and serves as the second output terminal Outb.

[0041] When the voltage value of the logic signal input by the first input terminal IN is at a high level, the NMOS transistor nlvt1 is tur...

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Abstract

The invention discloses a level conversion circuit. The level conversion circuit comprises an input sub-circuit, a first voltage supply sub-circuit, a second voltage supply sub-circuit and an output sub-circuit, wherein the first voltage providing sub-circuit is used for communicating the input sub-circuit and the output sub-circuit and providing adaptive drain voltage for a CMOS (complementary metal oxide semiconductor) tube in the input sub-circuit; the second voltage providing sub-circuit is coupled with the first output end and the second output end, and is suitable for providing bias voltage for the first voltage providing sub-circuit based on level values of logic signals output by the first output end and the second output end; the high level values of the logic signals output by the first output end and the second output end are larger than the high level values of the first logic signal and the second logic signal. By applying the scheme, the reliability of the low-voltage CMOS tube in the level conversion circuit can be improved.

Description

technical field [0001] The invention relates to the field of electronic circuits, in particular to a level conversion circuit. Background technique [0002] A semiconductor memory usually has a level conversion circuit for converting a low-voltage logic signal into a high-voltage logic signal. [0003] figure 1 It is a schematic structural diagram of a conventional level conversion circuit 10 . like figure 1 As shown, the level conversion circuit 10 includes: PMOS transistors phvt1-phvt4, and NMOS transistors nlvt1 and nlvt2. Among them, the PMOS transistors phvt1-phvt4 are high-voltage CMOS transistors, and the NMOS transistors nlvt1 and nlvt2 are low-voltage CMOS transistors. [0004] Taking the voltage value output by the power supply voltage output terminal VDDIO as 1.8V as an example, in the above-mentioned level conversion circuit 10, the drain voltages of the NMOS transistors nlvt1 and nlvt2 will reach above the nominal voltage (0.8V), which will make the NMOS Th...

Claims

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Application Information

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IPC IPC(8): H03K19/0185
CPCH03K19/0185
Inventor 马丽娜耿彦
Owner SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORP