Simulation ending mechanism based on UVM verification platform

Abstract

The invention discloses a simulation ending mechanism based on a UVM verification platform. Simulation ending control logic is written in a callback method in a score board assembly of a UVM; calling a callback method to obtain a target phase; and executing the simulation ending control logic on the target phase, wherein the simulation ending control logic is used for performing simulation ending control on the target phase. According to the method, the defect of inaccurate simulation ending control in the prior art is overcome, the method has the characteristics of accurate simulation ending control and high verification work efficiency, the problem debugging difficulty is reduced, and the simulation operation of the UVM is conveniently controlled.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a simulation end mechanism based on a UVM verification platform. Background technique [0002] In the prior art, the UVM (Universal Verification Methodology) verification methodology is usually used to verify the RTL (Register Transfer Level). When the phase mechanism is used for simulation operation, the user usually controls the UVM simulation process by setting an additional waiting time. Specific as figure 1 As shown, first call the find_by_name method of the phase mechanism in the end_of_elaboration_phase of the test case base class to obtain the target phase, and then call the set_drain_time method in phase_done to set the extra simulation end waiting time of the target phase. However, the DUT (Device under test) component The processing delay of the internal logic is in units of clock cycles, and the extra waiting time for the end of the target phase specified i...

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Problems solved by technology

[0002] In the prior art, the UVM (Universal Verification Methodology) verification methodology is usually used to verify the RTL (Register Transfer Level). When the phase mechanism is used for simulation operation, the user usually controls the UVM simulation process by setting an additional waiting time. Specific as figure 1 As shown, first call the find_by_name method of the phase mechanism in the end_of_elaboration_phase of the test case base class to obtain the target phase, and then call the set_drain_time method in phase_done to set the extra simulation end waiting time of the target phase. However, the DUT (Device under test) component The processing delay of the internal logic is in units of clock cycles, and the extra waiting time for the end of the target phase specified in the prior art is in units of the simulation time of the EDA (Electronic design automation) tool, so the prior art does not have The defect of inaccurate control at the end of the simulation. If the additional waiting time is set too long, then too long meaningless simulation time will be added, which will undoubtedly reduce the efficiency of the verification work. If the additional waiting time is set too short, it may Due to different DUTs, some additional waiting time is sufficient, and some are not enough. It is difficult to determine a unified waiting time. If there is a problem at this time, it will increase the difficulty of debugging the problem.

[0003] Moreover, in the prior art, the extra waiting time for the end of the target phase set by the set_drain_time of the test case base class will be determined in the project compilation phase, but the designs provided by many IP suppliers are provided in a pre-compiled form, which is difficult Require the other party to set the extra waiting time for the end of the target phase that is just right for this project during the pre-compilation period, so in this application scenario, the existing solution becomes no longer feasible

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