Simulation domain near memory computing array structure based on magnetic random access memory

Abstract

The invention discloses an analog domain near memory calculation array structure based on a magnetic random access memory (MRAM). The analog domain near memory calculation array structure comprises a transistor 1, a magnetic tunnel junction 1 (1T1M) storage array, a read-write circuit, a row decoding drive circuit, a data input unit, a pulse generation circuit, a current mirror integration module, an analog-to-digital converter, a shift addition circuit, a time sequence control circuit and a mode selection module. The method has a standard read-write mode and a near memory calculation mode. The read-write operation of data in the storage array is realized in the standard read-write mode; in a near memory calculation mode, a 1T1M memory unit is utilized to improve the equivalent magnetic resistance ratio (TMR) of an MRAM, multi-bit multiplication accumulation in neural network calculation is completed by using current integration while data is read, and meanwhile, calculation modules are arranged near a memory array, so that the memory array is not changed, the memory access energy consumption is reduced, and the memory access efficiency is improved. Compared with a traditional Von Noiemann framework neural network accelerator, the Von Noiemann framework neural network accelerator effectively improves calculation precision and circuit energy efficiency, and is compatible with an existing storage structure.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a magnetic random access memory (MRAM)-based near-storage calculation array structure in an analog domain and a circuit design method for realizing multi-bit multiply-accumulate calculation based on memory. Background technique [0002] In recent years, the rapid development of data-intensive technologies such as deep learning and big data terminals has put forward higher requirements for the data throughput and computing speed of computing units and memories. In the traditional von Neumann architecture, the memory and computing unit are two independent parts. The power consumption and speed limitations brought about by the data transfer between the memory and computing unit have become the bottleneck of the further development of modern computers. At the same time, a large amount of data generated in the calculation requires a large area of ​​memory to store,...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a magnetic random access memory-based analog domain near-memory computing array structure to solve the technical problems of MRAM-based analog domain near-memory computing TMR on the low side and analog near-memory computing non-linearity

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