Analog domain CIM (computing in memory) array structure based on magnetic random access memory

A random access memory, computing array technology, applied in static memory, digital memory information, computing and other directions, can solve the problems of non-linearity of analog memory calculation, low TMR, etc., to improve the equivalent TMR, improve the accuracy rate, the accuracy rate boosted effect

Pending Publication Date: 2021-10-01
SOUTHEAST UNIV
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Problems solved by technology

[0004] The purpose of the present invention is to provide a magnetic random access memory-based analog domain in-memory computing array structure to solve the technical problems of MRAM-based analog domain in-memory computing with low TMR and analog in-memory computing non-linearity

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  • Analog domain CIM (computing in memory) array structure based on magnetic random access memory
  • Analog domain CIM (computing in memory) array structure based on magnetic random access memory
  • Analog domain CIM (computing in memory) array structure based on magnetic random access memory

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[0091] An MRAM-based analog domain computing array structure described in the present invention includes a 6T2M storage array, a read-write circuit, a row decoding drive circuit, a data input unit, a pulse generation circuit, a current mirror integration module, an A / D converter, a shift A bit addition circuit, a timing control circuit and a mode selection module.

[0092] Such as figure 1 The analog domain storage computing array shown includes: 6T2M storage units are arranged in a matrix, and in the read-write mode, it realizes the storage function equivalent to the 2T2M storage array; in the calculation mode, it realizes the in-memory computing function equivalent to the 1T1M storage array; The decoding driving circuit and the reading and writing circuit are used for row and column decoding and data reading and writing of the storage array in the reading and writing mode; the data input unit and the pulse generating circuit realize the input of activation data in the calcul...

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Abstract

The invention discloses an analog domain CIM (computing in memory) array structure based on a magnetic random access memory (MRAM). The analog domain CIM (computing in memory) array structure comprises a 6-transistor 2-magnetic tunnel junction (6T2M) storage array, a read-write circuit, a row decoding driving circuit, a data input unit, a pulse generation circuit, a current mirror integration module, an analog-to-digital (A / D) converter, a shift addition circuit, a time sequence control circuit and a mode selection module. The method has a standard read-write mode and an in-memory calculation mode. The read-write operation of data in the storage array is realized in the standard read-write mode; in the in-memory calculation mode, a 6T2M storage unit is utilized, so that the equivalent magnetic resistance ratio (TMR) of the MRAM is improved; multi-bit multiplication accumulation in neural network calculation is completed through current integration while data is read, and meanwhile, a calculation module and a storage array are integrated together, so that memory access energy consumption is reduced; and compared with a traditional Von Noremann architecture neural network accelerator, the calculation precision and the circuit energy efficiency are effectively improved.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to a magnetic random access memory (MRAM)-based analog domain in-memory calculation array structure and a circuit design method for realizing multi-bit multiply-accumulate calculation based on the memory. Background technique [0002] In recent years, the development of artificial intelligence and machine learning has brought a large amount of data and calculations, which put forward higher requirements for the throughput and speed of computing units and memories. In the traditional von Neumann architecture, the memory and the computing unit are two independent parts. The traditional digital accelerator can only accelerate the computing unit, which will cause the speed mismatch between the computing unit and the memory. At the same time, a large amount of data generated in the calculation requires a large area of ​​memory to store, and the increase in the area of...

Claims

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Application Information

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IPC IPC(8): G06F7/544G11C11/16
CPCG06F7/5443G11C11/161G11C11/1673G11C11/1675G11C11/1653Y02D10/00
Inventor 蔡浩郭亚楠
Owner SOUTHEAST UNIV
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