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Semiconductor device

A semiconductor and transistor technology, applied in the field of semiconductor devices, can solve problems such as thermal runaway and temperature rise

Pending Publication Date: 2022-05-20
MURATA MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

There is an increase in collector current leading to a further rise in temperature, eventually reaching thermal runaway

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0032] refer to Figures 1 to 4D The accompanying drawings describe the semiconductor device of the first embodiment.

[0033] figure 1 It is a diagram showing the positional relationship of electrodes and wirings in a plan view of the semiconductor device according to the first embodiment. On one surface (hereinafter referred to as an upper surface) of a first member such as a semiconductor substrate, a plurality of transistors 20 having substantially the same characteristics are arranged in one direction. Each of the plurality of transistors 20 is, for example, a heterojunction bipolar transistor (HBT), and the plurality of transistors 20 are connected in parallel to each other. A structure in which a plurality of transistors having substantially the same characteristics are connected in parallel is called a multi-cell structure.

[0034] A passive element 25 is arranged between two adjacent transistors 20 . Each passive element 25 is electrically connected to one of the...

no. 2 example

[0080] Next, refer to Figure 5 , Figure 6A as well as Figure 6B , the semiconductor device of the second embodiment will be described. Below, for and reference Figures 1 to 4D The description of the structure common to the semiconductor device of the first embodiment described in the drawings is omitted.

[0081] Figure 5 It is a diagram showing the positional relationship of electrodes and wiring in a plan view of the semiconductor device according to the second embodiment. In the first embodiment, the passive element 25 ( figure 1 ) includes the input capacitor Cin and the ballast resistance element Rb, but in the second embodiment, the passive element 25 includes the emitter-base capacitor Ceb.

[0082] An electrode 32EB included in the second wiring layer is arranged between the two transistors 20 . The first-layer base wiring 31B extends to a region overlapping with the electrode 32EB in plan view. An emitter-base capacitor Ceb is formed in a region where the...

no. 3 example

[0096] Next, refer to Figure 7 , Figure 8A as well as Figure 8B , the semiconductor device of the third embodiment will be described. Below, for and reference Figure 5 , Figure 6A as well as Figure 6B The description of the structure common to the semiconductor device of the second embodiment described will be omitted.

[0097] Figure 7 It is a diagram showing the positional relationship of electrodes and wiring in a plan view of the semiconductor device according to the third embodiment. In the second embodiment, the passive element 25 ( Figure 5 ) includes an emitter-base capacitor Ceb, but in the third embodiment, the passive element 25 includes a base-collector capacitor Cbc and a base-collector resistance element Rbc.

[0098] The base-collector capacitor Cbc includes a lower electrode 31BC included in the first wiring layer, an upper electrode 32BC included in the second wiring layer, and a second interlayer insulating film 42 disposed therebetween. ( ...

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PUM

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Abstract

The invention provides a semiconductor device which includes a plurality of semiconductor elements and is suitable for miniaturization. A plurality of transistors are arranged in one direction on one surface of a substrate, and the transistors are connected in parallel with each other. Each of the plurality of transistors includes a collector layer, a base layer, and an emitter layer stacked in this order from the substrate side. A passive element is disposed in each of at least one of regions between two adjacent transistors among the plurality of transistors. A collector electrode electrically connected to the collector layer is disposed between the collector layer of each of the plurality of transistors and the substrate.

Description

technical field [0001] The present invention relates to semiconductor devices. Background technique [0002] A heterojunction bipolar transistor (HBT) is used as a high-frequency power amplifier mounted in a mobile terminal. The self-heating of the HBT increases due to the higher output of the power amplifier. When the temperature of the HBT rises due to self-heating, the collector current increases. There are cases where an increase in collector current causes a further rise in temperature, eventually reaching thermal runaway. [0003] In order to suppress the thermal runaway of the HBT, it is desired to improve the heat dissipation characteristics of the HBT. Patent Document 1 below discloses a semiconductor device that suppresses an increase in chip area and has high heat dissipation characteristics. The semiconductor device disclosed in Patent Document 1 includes a plurality of HBTs arranged in a row on a substrate made of semi-insulating GaAs or the like and connect...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L27/06H01L29/737H01L23/367
CPCH01L27/0207H01L27/0211H01L27/0647H01L27/0658H01L29/737H01L29/7371H01L23/367H01L21/8252H01L27/0248H01L25/50H01L25/0655H01L25/16H01L2224/24137H01L29/861H01L29/20H01L25/18H01L25/0657H01L27/0255H01L24/05H01L2224/1357H01L2224/08H01L2224/08145H01L24/24H01L2224/24146H01L24/13H01L2224/13147H01L2224/05644
Inventor 高桥新之助青池将之筒井孝幸小屋茂树
Owner MURATA MFG CO LTD