Function verification method and system of clock domain crossing asynchronous circuit and computer readable storage medium

Abstract

The invention provides a function verification method and system for a clock domain crossing asynchronous circuit and a computer readable storage medium. The method comprises the steps that a hardware description language is used for describing design codes of the clock domain crossing asynchronous circuit; developing a software tool to analyze and process the design code so as to realize functional simulation of a metastable state phenomenon appearing and / or disappearing in the clock-crossing asynchronous circuit; and carrying out function verification on the test case by using the analyzed and processed design code, so as to discover the design problem existing in the cross-clock asynchronous circuit. By processing the asynchronous circuit design code, the simulation of the asynchronous circuit design abnormity is realized, and the verification efficiency is improved while the verification cost is reduced.

Description

Technical field [0001] The present invention relates to the field of computer technology, in particular to a functional verification method for trans-clock domain asynchronous circuit design portion of a chip, a system and a computer-readable storage medium. Background [0002] In the design of chip digital circuits, if there is a cross-clock domain asynchronous circuit design in the design part, then the design of this part needs to be paid attention to, and designers usually use some special methods to avoid functional errors caused by the circuit entering the metastable state during operation. However, if the designer fails to notice a cross-clock domain problem in the design, or employs a wrong circumvention method, it is impossible to avoid the circuit entering a metastable state and leading to functional errors. [0003] Since the timing information of the circuit is not considered during the existing functional simulation phase, this erroneous asynchronous circuit design c...

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Problems solved by technology

However, if the designer fails to notice that there are clock domain crossing problems in the design, or uses the wrong workaround method, then there is no way to prevent the circuit from going into metastable state and causing malfunction

[0003] Since the timing information of the circuit is not considered in the existing functional simulation stage, this kind of wrong asynchronous circuit design cannot be found in ordinary functional verification

Although the follow-up timing simulation can find problems in the design of asynchronous circuits across clock domains, because the current design is getting larger and larger, the time cost of timing simulation is too huge, and only a small number of test cases can be run; It also introduces unreasonable timing constraints, which can cause some cross-clock domain asynchronous circuit design problems to be masked

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