Templated memory test pattern generator and method

Abstract

The invention discloses a templated memory test pattern generator and method, the templated memory test pattern generator comprises a test processor, a simple storage test pattern generator, a channel time sequence and waveform generator and an electronic pin, the simple storage test pattern generator comprises an X address generator, a Y address generator, a D data generator and an SMPG and channel mapping, the inlet wire end of the channel time sequence and waveform generator is in mapping connection with the SMPG and the channel, and the outlet wire end of the channel time sequence and waveform generator is connected with the electronic pin; and the parallel data calculated by the simple storage test pattern generator according to the SMPG resource mapping table provided by the upper computer and the pins of the tested device are in one-to-one mapping. The number of the test vectors in the image file can be effectively reduced. Meanwhile, after the scheme is templated, the reuse rate of a test program can be improved, and the development period of the test scheme is shortened.

Description

technical field [0001] The invention relates to a templated memory testing pattern generator and method, belonging to the fields of integrated circuit automatic testing equipment, semiconductor manufacturing, instrumentation, digital signal, mixed-signal chip testing, high-speed signal testing and the like. Background technique [0002] In the test scenario for memory, testing such devices often has two characteristics: [0003] 1. There are many device pins, mainly address pins and data pins with wider digits; [0004] 2. The amount of data to be tested is very large, because the storage capacity of the memory is large, and the test needs to traverse all the storage units to avoid dead pixels. [0005] Traditional test solutions such as figure 1 Shown: Graphic file (Pattern), which records the level state and timing of all pins under each cycle. The pattern generator (Pattern Generator, Pat Gen for short) is responsible for sending instructions to the pin generator (Pin ...

AI Technical Summary

Problems solved by technology

Therefore, this test method is very inefficient in memory testing, and the error rate of writing and modifying patterns is very high

The traditional method relies on the test vectors in the graphics file to represent the level status of the pins of the device under test in each cycle, so with the increase of the pins of the device under test and the increase in memory capacity, the test vectors in the graphics file will become The multiplier increases, which affects the test efficiency and increases the difficulty of writing and modifying graphic files

[0008] In addition, relying solely on graphic files to statically represent test vectors limits the reusability of test solutions

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