Programmable circuit, integrated circuit and electronic equipment

Abstract

The invention discloses a programmable circuit, an integrated circuit and electronic equipment, and belongs to the technical field of integrated circuits. The programmable circuit comprises a signal conversion module which converts a parallel signal input by an external circuit into a serial signal; the signal configuration module shifts the phase of the serial signal output by the signal conversion module by 0 degree or 360 degrees; the first enable signal generation module is used for generating a first enable signal; the DDR configuration module is used for generating a second enable signal; setting a DDR mode of the programmable circuit; the phase monitoring module is used for monitoring the phase of a DQS signal input by an external circuit and outputting a monitoring result; and the phase adjustment module adjusts the phase of the first enable signal generated by the first enable signal generation module according to the monitoring result input by the external circuit. According to the invention, the offset state of the DQS signal is monitored in real time and corrected in real time, the unit time interval of the DQS gate is expanded, errors caused by sampling DQ data by the DQS are avoided, and the setting of three modes of DDR3, DDR4 1tCK and DDR4 2tCK is realized through the DDR configuration module.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and in particular, to a programmable circuit, an integrated circuit and an electronic device. Background technique [0002] In DDR (Double Data Rate, double-rate synchronous dynamic random access memory) memory, the DQS signal of DDR3 / 4 (third and fourth generation DDR) will be in a high-impedance state during read and write switching, so it needs to pass the DDR PHY (port physical layer) to generate a DQS_gate (DQS window) to avoid the high impedance state of the DQS signal and prevent bit errors when DDR3 / 4 reads data. [0003] DDR PHY (port physical layer) uses an adjustable delay internal signal rxena (enable signal) to sample the DQS signal returned by reading, returns a bit signal sample, adjusts the delay of rxena through the DQS Gate training algorithm, and then judges consecutive samples value to determine the position of the first rising edge of the read return DQS ...

AI Technical Summary

Problems solved by technology

[0006] The purpose of the present invention is to provide a programmable circuit, integrated circuit and electronic equipment to solve the problem that DQS_gate has only half a UI when the existing circuit solves the DQS signal offset, and cannot detect the DQS signal offset in real time and correct it in real time, so as to further solve the problem. A single technical issue for the DDR mode of the circuit

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