ISP receiver capable of compatibly processing PLL and DLL modes

Abstract

An ISP receiver compatible with PLL and DLL processing modes comprises a bypass frequency division module and a phase-locked loop connected with the bypass frequency division module, and the phase-locked loop comprises a phase frequency detector, a charge pump, a low-pass filter and a voltage-controlled oscillator which are connected in sequence; the clock data recovery module is connected with the low-pass filter and the voltage-controlled oscillator; the bypass frequency division module has the functions that when an input signal is in a DLL mode, the input signal is directly output to the phase-locked loop; when the input signal is in a PLL mode, the input signal is output to the phase-locked loop after being subjected to four-frequency division; and the clock data recovery module can select a corresponding working mode according to the input signal. By setting the working mode of the bypass frequency division module and cooperating with the corresponding configuration of the clock data recovery module, compatible processing of two modes of DLL and PLL can be realized.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, relates to display signal processing, and in particular relates to an ISP receiver compatible with processing PLL and DLL modes. Background technique [0002] ISP (Intergrated-Stream Protocol) is a high-speed serial interface protocol defined by the display driver chip manufacturer for the clock embedded in the system. The receiving end needs to recover the clock data in the data (CDR: clock data recovery). The ISP protocol defines two working modes: DLL and PLL. The training modes of the two modes are different. The specific performance is that the training clock signals used are inconsistent, such as image 3 The training clocks for these two modes are given as shown, image 3 Among them, in PLL mode [1], [2] are a full cycle of a signal, in DLL mode, [1], [2]…[8] are a full cycle of a signal. [0003] The existing ISP receiver is designed to only be used in PLL mode or DLL mode. Du...

AI Technical Summary

Problems solved by technology

[0003] Existing ISP receivers are designed to only be used in PLL mode or DLL mode, and the test requires the transmitter to cooperate with the corresponding mode to work normally. The voltage-controlled oscillator VCO in DLL mode is a low-frequency multi-phase output; PLL mode The high-frequency and low-phase output of the voltage-controlled oscillator VCO makes the PLL mode architecture and DLL mode architecture incompatible, and cannot handle both modes at the same time

Images