Polynomial hardware multiplier based on Saber key packaging and use method

A technology of polynomials and multipliers, applied in instruments, digital data processing components, calculations, etc., can solve problems that are not suitable for lightweight implementation, multiple hardware resources, consumption, etc.

Pending Publication Date: 2022-07-22
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A similar "divide and conquer" algorithm replaces multiplication with addition and subtraction in hardware implementation, which can reduce the number of cycles, but will require more pre-processing and post-processing steps, s

Method used

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  • Polynomial hardware multiplier based on Saber key packaging and use method
  • Polynomial hardware multiplier based on Saber key packaging and use method
  • Polynomial hardware multiplier based on Saber key packaging and use method

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Embodiment Construction

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] The embodiments of the present invention are aimed at the lightweight schoolbook polynomial hardware multiplier of the Saber key encapsulation scheme, such as figure 1shown. The figure shows the overall architecture of the lightweight parallel schoolbook polynomial multiplication circuit design.

[0025] When the single polynomial multiplication starts, the control module will first determine whether the current polynomial multipl...

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Abstract

The invention provides a polynomial hardware multiplier based on Saber key packaging and a use method. The polynomial hardware multiplier comprises an addressing circuit, a public polynomial data loading module, a coefficient multiplication and accumulation circuit and a control module. The control module controls the overall state trend and provides address indexes of two multipliers for the addressing circuit. A first storage unit outputs 64-bit data, two continuous coefficient streams can be stably obtained through a common polynomial data loading module, meanwhile, the two coefficient streams of a secret polynomial can be directly read out from a second storage unit according to an address, the low 3-bit absolute value of the two secret polynomials and 0 of 13 bits form a 19-bit Coms signal, and the 19-bit Coms signal is transmitted to the second storage unit. And the three paths of signals enter a coefficient multiplication and accumulation circuit for operation. According to the method, frequent reading and writing of the cycle of the accumulated result are avoided, the polynomial multiplier does not need to be paused, and the operation time is shortened under the conditions that the hardware resource consumption is kept basically unchanged and the same low power consumption is kept.

Description

technical field [0001] The invention belongs to the technical field of information security encryption, in particular to a polynomial hardware multiplier based on Saber key encapsulation and a method for using the same. Background technique [0002] After the emergence of Shor's quantum algorithm, traditional public key encryption schemes such as RSA (asymmetric encryption) and ECC (elliptic curve encryption) have been greatly threatened, and there is a possibility of being broken by quantum computers in polynomial time. There are three key encapsulation schemes based on lattice, Saber key encapsulation scheme is one of them. The security of Saber is based on Module-Learning with Rounding (M-LWR) with rounding problem, which is obtained by F-O transformation of public key encryption primitives. In Saber, since the modulus is a power of 2, the rounding method can be used to transform the modulus domain to introduce random errors, thus reducing the volume of the ciphertext an...

Claims

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Application Information

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IPC IPC(8): G06F7/523G06F21/60
CPCG06F7/523G06F21/602
Inventor 刘伟强章渊拓崔益军徐天宇倪子颖王成华
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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