Contact hole etching method of CMOS device and CMOS device manufacturing method

Abstract

The invention provides a contact hole etching method of a CMOS (Complementary Metal Oxide Semiconductor) device and a manufacturing method of the CMOS device, which are characterized in that after a device layer is formed through a front-end process, an etching stop layer is formed on a grid electrode and an active region of the device layer, a carbon cap layer is formed on the etching stop layer, or a carbon-rich layer is formed on the surface layer of the etching stop layer through ion implantation carbon in the etching stop layer, and the carbon cap layer is formed on the surface layer of the carbon-rich layer. And forming an interlayer dielectric layer on the etching stop layer. Due to the existence of the carbon cap layer or the carbon-rich layer above the etching stop layer, when the etching stop layer with relatively shallow depth is etched, a large amount of polymer is formed in the etching stop layer, and the polymer can protect the etching stop layer to be further etched. Therefore, in the subsequent etching process of the contact hole with the relatively deep depth, the contact hole with the relatively shallow depth can be effectively protected from an over-etching phenomenon until the etching of the contact hole with the relatively deep depth is completed. Therefore, the over-etching phenomenon is avoided, the deep contact hole can be fully etched, and the phenomenon of insufficient etching is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a method for etching a contact hole of a CMOS device and a method for manufacturing the CMOS device. Background technique [0002] In semiconductor devices, contacts are typically formed on the gate and active regions (ie, source or drain). In CMOS devices, the contacts on the active area are usually deeper than the contacts on the gate. In other advanced technologies, such as FDSOI (fully depleted silicon-on-insulator) and 3D NAND, there are contacts with different depths of contact with the active area. [0003] In the prior art, contact holes in semiconductor devices are usually formed by simultaneous etching. At this time, for gates and active regions with different depths, there will be contact holes with a shallow depth and over-etching will occur, and contact holes with a shallow depth will be under-etched. Whether it is over-etching or under-etching, the conductivi...

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Problems solved by technology

[0004] Therefore, there is an urgent need for a method that can solve the problem of over-etching and under-etching in contact holes with different depths without causing a significant increase in device cost.

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