Transistor device and manufacturing method thereof
A technology of transistors and transistor units, used in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc.
Pending Publication Date: 2022-08-05
INFINEON TECH AG
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- Abstract
- Description
- Claims
- Application Information
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Problems solved by technology
While cost can be reduced by shrinking device geometries, various trade-offs and challenges must be met when increasing device functionality per unit area
For example, shrinking device geometries can be accompanied by challenges in terms of meeting requirements for heat dissipation per unit die area, device reliability, or switching speed
Method used
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[0011] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which specific examples in which semiconductor substrates may be processed are shown by way of illustration. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example can be used on or in combination with other examples to yield further examples. The present disclosure is intended to include such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only. Corresponding elements in the different figures are designated by the same reference numerals if not stated otherwise.
[0012] The terms "having", "comprising", "in...
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Transistor devices and methods of manufacturing the same are disclosed. A transistor device (10) is presented. An example of a transistor device (10) includes a semiconductor body (100) having a first main surface (101), a second main surface (102) opposite the first main surface (101). The transistor device (10) further includes a transistor cell array (610) including a plurality of transistor cells (TCs). The transistor cell array (610) includes a first load electrode (L1) on the first main surface (101). The first load electrode (L1) is electrically connected to the plurality of transistor cells (TC). The transistor cell array (610) further includes a second load electrode (L2) on the second major surface (102). The second load electrode (L2) is electrically connected to the plurality of transistor cells (TC). The plurality of transistor cells (TC) comprises at least one control electrode (C) comprising carbon.
Description
technical field [0001] The present disclosure relates to transistor devices and methods of fabricating transistor devices, and more particularly to transistor devices including a plurality of transistor cells including a control electrode. Background technique [0002] Technological developments in next-generation transistor devices, such as insulated gate field effect transistors (IGFETs) such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), have focused on improvements by reducing device geometries electrical device characteristics and reduce costs. While cost can be reduced by reducing device geometry, various tradeoffs and challenges must be met when increasing device functionality per unit area. For example, shrinking device geometries may be accompanied by challenges in terms of meeting requirements for heat dissipation per unit chip area, device reliability, or switching speed. [0003] There may be a des...
Claims
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Patent Timeline
Login to View More IPC IPC(8): H01L29/423H01L29/49H01L29/739H01L29/78H01L21/28H01L21/336H01L21/331
CPCH01L29/7827H01L29/7398H01L29/7397H01L29/66068H01L29/401H01L29/42312H01L29/4236H01L29/49H01L29/0696H01L29/407H01L21/049H01L29/1608B82Y10/00H01L29/1095H01L29/417H01L29/7813H01L25/072H01L29/495H01L29/78
Inventor R·西门尼克I·穆里T·施洛瑟H-J·舒尔茨O·斯托贝克
Owner INFINEON TECH AG