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Semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of device performance impact, process realization, side wall damage, etc., so as to reduce the impact and reduce the occurrence probability of over-etching , to avoid the effect of over etching

Pending Publication Date: 2022-08-09
SHANGHAI HUALI MICROELECTRONICS CORP
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Problems solved by technology

[0004] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, so as to solve the problem that the existing process for forming the sidewall structure in the semiconductor structure will cause damage to the sidewall, thereby affecting the realization of the subsequent process, resulting in the final formed device performance-affected issues

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  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof
  • Semiconductor structure and manufacturing method thereof

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Embodiment Construction

[0028] As described in the background art, during the process of forming the sidewall structure, the sidewall material layers formed on the memory cell area and the logic circuit area are etched twice continuously, which is prone to over-etching and damages the sidewalls (such as Figure 1C shown). Therefore, the realization of the subsequent process is affected, the performance of the finally formed device is affected, and the yield and reliability of the device are affected. The present embodiment provides a semiconductor structure and a method for manufacturing the same. Only one etching process is performed on the logic circuit region to avoid over-etching, protect the sidewall structure from damage, and ensure that subsequent processes are not affected, thereby helping Improve device yield and reliability. At the same time, the occurrence probability of over-etching can also be reduced for the memory cell region, thereby effectively reducing the influence of the etching ...

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Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. According to the semiconductor structure manufacturing method provided by the invention, a first oxide layer and a silicon nitride layer are formed in a storage unit region and a logic circuit region; then, protecting the logic circuit region, and executing a first etching process on the storage unit region to remove the silicon nitride layer on the top of the gate structure and the substrate in the storage unit region; and then, depositing a second oxide layer in the memory cell region and the logic circuit region, and executing a second etching process on the memory cell region and the logic circuit region so as to form a side wall of an ONO structure on the side wall of the gate structure in the memory cell region and the logic circuit region. According to the manufacturing method provided by the invention, the etching process is only executed once on the logic circuit region, so that the over-etching is effectively prevented, the side wall structure is protected from being damaged, the subsequent process is ensured not to be influenced, and the yield and the reliability of the device are improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof. Background technique [0002] The existing method for forming a spacer structure in a semiconductor device includes: step 1, providing a substrate, the substrate 100 includes a memory cell region A and a logic circuit region B, and both the memory cell region A and the logic circuit region B are distributed with multiple gate structures (such as Figure 1A shown); step 2, depositing a layer of spacer material on the substrate and the gate structure, such as Figure 1B As shown, the sidewall material layer includes, for example, a first oxide layer 310, a silicon nitride layer 320 and a second oxide layer 500 (ONO structure); in step 3, the top and sidewalls of the substrate and the gate structure are removed by etching. side wall material layer. However, after step 3 is completed, especial...

Claims

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Application Information

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IPC IPC(8): H01L27/11531H01L27/11521H01L27/11526
CPCH10B41/40H10B41/42H10B41/30
Inventor 郑鸿柱张利东
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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