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Semiconductor memory and semiconductor memory control method

A semiconductor and memory technology, applied in the field of semiconductor memory, can solve the problems that the average current consumption cannot be effectively reduced, and the current consumption of peripheral circuits cannot be reduced by the leakage current flowing through the word line.

Inactive Publication Date: 2005-08-17
PS4 LUXCO SARL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] However, there is also a problem that the average current consumption of the entire DRAM cannot be effectively reduced because only setting the bit line to a floating state cannot reduce the leakage current flowing through the word line and the current consumption of peripheral circuits, etc.

Method used

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  • Semiconductor memory and semiconductor memory control method
  • Semiconductor memory and semiconductor memory control method
  • Semiconductor memory and semiconductor memory control method

Examples

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no. 1 example

[0035] figure 1 The configuration of the semiconductor memory according to the first embodiment of the present invention is shown. Specifically, figure 1 A typical configuration of a DRAM is shown.

[0036] Such as figure 1 As shown, the semiconductor memory according to the first embodiment includes: a power supply circuit section 1 including internal voltage generator circuits respectively for generating predetermined internal power supply voltages; and a DRAM storage section 2 including a memory array unit for holding data and control circuits.

[0037] The power supply circuit part 1 includes: VPP internal voltage generator circuit 11 (VPPGENE.), used to generate word line voltage VPP; VBB internal voltage generator circuit 12 (VBBGENE.), used to generate memory array substrate voltage VBB; VBLR internal The voltage generator circuit 13 (VBLR GENE.) is used to generate the bit line precharge voltage VBLR; the VPLT internal voltage generator circuit 14 (VPLT GENE.) is u...

no. 2 example

[0084] Figure 13 A semiconductor memory configuration according to a second embodiment of the present invention is shown.

[0085] In the second embodiment, the VPP internal voltage generator circuit 11 for generating the word line voltage VPP is not stopped according to the internal power supply stop signal GOFF output from the internal power supply control circuit 43 . Furthermore, in the second embodiment, the word line voltage is applied to the source and substrate of each pMOS in the word driver applying the word line voltage VPP and the logic circuit in the X decoder, etc., respectively, as Figure 13 shown. Furthermore, a switching transistor Q100 is provided between the output terminal of the VPP internal voltage generator circuit 11 and the source of the pMOS transistor for disconnecting them. The rest of the configuration of the semiconductor memory according to the second embodiment is similar to that of the first embodiment, and thus will not be described.

[008...

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Abstract

In a semiconductor memory device which requires a refresh operation, a control method stops supplying a word line voltage which is a boosted voltage higher than an external supply voltage, a memory array substrate voltage which is a negative voltage supplied to a semiconductor substrate, and a bit line precharge voltage for use in reproducing data held in memory cells for a predetermined period at the end of each refresh operation. In this event, voltage output terminals of the word line and memory array substrate voltages are respectively driven to a ground potential. For recovering these voltages, the delivery of the word line voltage is stopped until the memory array substrate voltage rises to some extent.

Description

technical field [0001] The present invention relates to a semiconductor memory control method suitable for application to a DRAM (Dynamic Random Access Memory) requiring a refresh operation, and a semiconductor memory. Background technique [0002] Recently, semiconductor memories such as DRAMs have also begun to be used in mobile terminal devices such as cellular phones, PDAs (Personal Digital Assistants), etc., and thus semiconductor memories are increasingly required to reduce current consumption. [0003] As a method of reducing current consumption, for example, Japanese Laid-Open Patent Application No. 8-203268 discloses a technique of setting a bit line to float during a non-access period for a memory cell holding data. set state to eliminate leakage current through the bit line and the sense amplifier connected to it, thereby reducing current consumption. The non-access cycle refers to a cycle excluding data read, data write, and refresh operation cycles. The refres...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/407G11C11/401G11C11/403G11C11/406G11C11/4074
CPCG11C11/4074G11C11/406G11C11/401
Inventor 桥本刚伊藤丰
Owner PS4 LUXCO SARL