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32-bit embedded microprocessor adopting double instruction set

A microprocessor and embedded technology, applied in the direction of concurrent instruction execution, machine execution device, etc., can solve the problems of slow execution speed and unrealistic, and achieve the effect of improving efficiency, increasing area and reducing power consumption

Inactive Publication Date: 2005-08-24
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The execution speed of the interpreted execution method is slow; compared with the interpreted execution, just-in-time compilation of JIT can improve the processing speed, but the occupied memory resources will increase by two to three orders of magnitude. Unrealistic; there are three common approaches to hardware direct execution:

Method used

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  • 32-bit embedded microprocessor adopting double instruction set
  • 32-bit embedded microprocessor adopting double instruction set
  • 32-bit embedded microprocessor adopting double instruction set

Examples

Experimental program
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Embodiment Construction

[0033] The present invention will be described in further detail below in conjunction with the accompanying drawings.

[0034] For the five-stage pipeline structure of RISC state and the six-stage pipeline structure of Java state, see figure 1 and figure 2 shown. in:

[0035] IF (fetch instruction), take the instruction out of the instruction memory and lock it in the latch of the IF / ID stage. The RISC state has the same function as the Java state;

[0036] ID (instruction decoding), in the RISC state, the instruction latched in the IF / ID stage is taken out for decoding, and the control signal of the subsequent stage is generated, and all control signals are locked in the latch of the ID / EXE stage, from Read the operands in the register file; in the Java state, perform instruction length interception, instruction folding, and instruction decoding to generate control signals in the subsequent stages. All control signals are locked in the latches of the ID / OF stage, and at ...

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PUM

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Abstract

The invention is a kind of 32 bits embedded micro-processor which uses the new structure; it can process the local RISC instruction and Java virtual machine instruction. It is made up of instruction taking unit, instruction cache, instruction coding circuit, instruction replicating circuit, universal register group, data calculating unit, memory unit, promoting circuit and abnormity processing unit. The injunction cache and injunction replicating circuit is useful only in executing the Java virtual machine, at the same time, the universal register group is mapped into stack cache. The inventions have two instructions repertories, they can be switches seamlessly, but the circuit area increases only no more than 20% compared with the old.

Description

technical field [0001] The invention relates to a 32-bit embedded microprocessor, which supports two instruction sets of local RISC instruction and Java card virtual machine. Background technique [0002] With the advent of the network era, network communication, information security and information home appliances will become more and more popular, and reusable IP core and SOC technology have also been valued and developed in this trend. As the core of SOC chip, embedded microprocessor is very critical to SOC design. The traditional 8-bit microprocessor has been widely used because of its small chip area and convenient development. But because its bus width is only 8 bits, its performance is relatively low. With the continuous expansion of applications such as wireless communications, handheld computers, network communications, digital audio players, and digital high-definition televisions, the system control part is becoming more and more complex, and the performance req...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F9/38
Inventor 徐科王文婷忻凌闵昊周晓方顾沧海
Owner FUDAN UNIV
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