Power semiconducter device with RESURF layer
A semiconductor and device technology, applied in the field of high-power semiconductor devices, can solve problems such as withstand voltage deviation
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no. 1 example
[0132] A semiconductor device according to a first embodiment of the present invention is explained using FIG. 2 . FIG. 2 is a cross-sectional view of a vertical power MOS transistor.
[0133] As shown in the figure, n + type drain layer 10 set n - n-type first drift layer 11, and an n-type second drift layer 19 is disposed on the first drift layer 11. The p-type base layer 12 is selectively arranged in the surface of the second drift layer, and the n-type base layer 12 is selectively arranged in the surface of the base layer 12. + Type source layer 13. The gate insulating film 14 is interposed between the second drift layer 19 and the base layer 12 between the adjacent source layers 13 to form the gate 15 . The grid 15 is provided in a striped planar pattern along a direction perpendicular to the paper surface of FIG. 2 . A source 17 is provided on the source layer 13 and the base layer 12 , and a drain 16 is provided on the back of the drain layer 10 . Furthermore, the...
no. 2 example
[0152] Next, a semiconductor device according to a second embodiment of the present invention will be described using FIGS. 4A to 4D . 4A is a cross-sectional view of a power MOS transistor according to the present embodiment. FIG. 4B and FIG. 4C show the impurity concentration profile in the depth direction of the drain layer of the MOS transistor shown in FIG. 4A , and FIG. 4D shows the depth direction profile in the drift layer. electric field distribution.
[0153] The MOS transistor according to the present embodiment has the same structure as the MOS transistor according to the first embodiment described above, as shown in FIG. 4A. That is, the carrier conducting layer has two regions of the super junction and the first drift layer 11 . Also, as shown in FIG. 4B , the impurity concentration is higher in the super junction than in the first drift layer 11 .
[0154] As shown in FIG. 4D , the intensity of the electric field distribution in the super junction and the firs...
no. 3 example
[0163] Next, a semiconductor device according to a third embodiment of the present invention will be described using FIGS. 5A to 5E . This embodiment explains the manufacturing method of the MOS transistor according to the first and second embodiments described above, and FIGS. 5A to 5E sequentially show cross-sectional views of the manufacturing process of the MOS transistor shown in FIG. 2 .
[0164] First, as shown in Figure 5A, at n + Type semiconductor substrate 10 is formed on n - type first drift layer 11 . Furthermore, an n-type semiconductor layer 19 a is formed on the first drift layer 11 .
[0165] Next, as shown in FIG. 5B, a mask material 20 is formed on the semiconductor layer 19a. And, the mask material 20 on the region where the RESURF layer should be formed is removed by photolithography and etching. Next, a p-type impurity such as B is introduced into the semiconductor layer 19a by ion implantation.
[0166] Subsequently, after removing the mask material...
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