Analysis method of repair state of redundant bit in DRAM

A dynamic random access, redundant bit technology, used in semiconductor/solid-state device manufacturing, semiconductor/solid-state device testing/measurement, electrical components, etc. Correctly fix bugs etc.

Inactive Publication Date: 2003-03-19
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above are all existing steps. However, after the redundant bit is repaired, it is often found that there are still defects in the DRAM, so it is impossible to determine whether the circuit design is good or bad; Know whether the defect has been repaired correctly, or whether the original correct array line has been replaced and repaired with redundant bits, but the problem of the defect has not been solved
If you want to determine whether the redundant bit repair is complete, you must go through repeated production of dynamic random access memory components (DRAM Cell) and continuous testing to verify whether the design is wrong (Try-and-error Method). Significantly increases process time and increases process complexity
[0008] In addition, as we all know, in order to solve the problem of whether the design is good or bad after the redundant bit is repaired, and whether the defect has been repaired correctly, a Design In Test Mode will be executed to Test the redundant bit data (Data) that has been repaired, otherwise it can only be verified by a large amount of data and repeated lasers (Laser), which is time-consuming and labor-intensive
However, this existing test mode is a big burden on cost because it will increase the area of ​​the chip

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  • Analysis method of repair state of redundant bit in DRAM
  • Analysis method of repair state of redundant bit in DRAM
  • Analysis method of repair state of redundant bit in DRAM

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Embodiment Construction

[0032] figure 2 It is a schematic diagram of an apparatus for analyzing redundancy repair (Redundancy Repair) of a dynamic random access memory (Dynamic RAM, DRAM for short) according to a preferred embodiment of the present invention.

[0033] Please refer to figure 2 , the device includes an automatic needle measuring machine 200 , a light source 202 and a convex lens 204 . Wherein, the wafer to be measured (Wafer) 206 is placed on the automatic pin tester 200, and the light source 202 is located above the automatic pin tester 200, and the convex lens 204 located between the automatic pin tester 200 and the light source 202 is used to concentrate the emitted light from the light source 202. The light beam 208 is focused on the wafer 206 to be aligned with the array (Array) part in the predictive die (Die). In order to use this device for analyzing redundant bit repair of dynamic random access memory in detail, and analyze whether the redundant bit repair of dynamic rando...

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Abstract

The analysis method of repair state of redundant bit in DRAM to detect whether the redundant bit to be repaired correctly is to irradiate the chip with one concentrated light beam and then to observe the physical bit image. When the beam is aims at the defected array position, two semi-circuit bright areas will be displayed in the screen. When the beam is aimed at the redundant bit for repairing the damaged array, one bright strip will be displayed in the screen. Based on the position of the bright strip and the two semi-circular bright areas, whether the repair aim is reached correctely may be detected.

Description

technical field [0001] The present invention relates to a method for analyzing dynamic random access memory (Dynamic RAM, referred to as DRAM), and in particular to a method for analyzing whether dynamic random access memory (Dynamic RAM, referred to as DRAM) redundancy (Repair) The correct way. Background technique [0002] In general, the array (Array) in the dynamic random access memory (Array) includes not only the normal array used for performing operations, but also includes redundant bits used to repair the defective array. This is because defects may occur in the array during the process of manufacturing the DRAM. The so-called "redundant bit" refers to making a few more rows (Row) or columns (Column) on the chip (Die). These rows or columns are usually useless, but when the array is defective, these redundant bits It will become an active (Active) array as a replacement for the defective array. See Figure 1A and Figure 1B . [0003] Fi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66H01L21/8242
Inventor 何明瑾
Owner UNITED MICROELECTRONICS CORP
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