Method and device for detecting information of memory

Abstract

Methods and apparatus for storing memory test information are presented. The method includes the steps of storing a portion of information related to locations and numbers of failed memory cells detected while testing memory, and updating the stored information as failed memory cells are detected to indicate a first type of memory spare is to be assigned to repair a failed memory cell, a second complementary type of memory spare is to be assigned to repair the failed memory cell, or the memory is not repairable. The first type of memory spare corresponds to one of a row and a column portion of memory and the second complementary type of memory spare corresponds to the other of the row and column portions of memory.

Description

[0001] related application [0002] This application claims priority under 35 U.S.C. §119(e) to U.S. Patent Application No. 60 / 296,789, entitled "Error Memory," filed June 8, 2001, the entire contents of which are incorporated in This is for reference. technical field [0003] Described are methods and apparatus for storing memory test information. In particular, methods and apparatus for storing memory test information for a memory having redundant memory circuits are described. Background technique [0004] Conventional memory testing involves identifying all failing memory addresses of a memory array and identifying which bit(s) of those memory addresses are failing. A typical memory test involves writing a data pattern in a memory, then reading the memory's output and comparing it to an expected value or pattern. The mismatch between the expected and actual read memory values ​​is stored in an external memory map, usually within the memory tester itself. [0005] Aft...

AI Technical Summary

Problems solved by technology

This requires the repair algorithm to "randomly" process faulty memory information, which as described above leads to ineffective use of redundant memory cells contained in the memory chip

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