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Semiconductor IC and mfg. method thereof

An integrated circuit and semiconductor technology, applied in the field of semiconductor integrated circuits, can solve problems such as increasing the test time, and achieve the effect of shortening the test time and preventing the increase of the chip size

Inactive Publication Date: 2003-05-28
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, there is a problem that when various tests are continuously performed, the command signal needs to be input many times, thereby increasing the test time

Method used

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  • Semiconductor IC and mfg. method thereof
  • Semiconductor IC and mfg. method thereof
  • Semiconductor IC and mfg. method thereof

Examples

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Embodiment Construction

[0023] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the figure, each signal line shown by a thick line includes a plurality of lines. Signals with a "Z" as the last letter indicate positive logic, and signals with a "B" or "X" as the last letter indicate negative logic.

[0024] FIG. 1 shows an embodiment of the semiconductor integrated circuit of the present invention. The semiconductor integrated circuit is formed on a silicon substrate by using CMOS processing as a clock asynchronous DRAM. The DRAM has a login circuit 14 including a login decoder 10 and a record generator 12, an address decoder 16, a test control circuit 18, a plurality of test start circuits 20 (20a, 20b, 20c, . . . ), an operation control circuit 22. and memory core 24 . In this figure, dots at the ends of the signal lines represent external terminals.

[0025] Login decoder 10 receives control command CMD (chip enable si...

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PUM

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Abstract

When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit with a test mode. Background technique [0002] As a semiconductor integrated circuit having a test mode, for example, a technique disclosed in Japanese Unexamined Patent Publication No. Hei 2000-243797 is known. When a test command is input multiple times in the normal operation mode, the semiconductor integrated circuit shifts to the test mode. Therefore, it is possible to prevent the semiconductor integrated circuit from accidentally shifting to the test mode during normal operation. [0003] However, for example, when various tests are performed after the semiconductor integrated circuit is manufactured, it is necessary to input a command signal multiple times for each test. It is also necessary to input the command signal a plurality of times to change the operation mode in the semiconductor integrated circuit from the test mode to the normal operation mode after each test. The...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G01R31/3181G01R31/3185G11C29/00G11C29/46H01L21/822H01L27/04
CPCG01R31/3181G11C29/46G11C29/00
Inventor 坪井浩庆藤冈伸也
Owner SOCIONEXT INC
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