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Encoding up/down based D-A converter and delayed phase locking loop device and method therefor

A technology of delay locked loop and analog converter, which is applied in the field of DAC and DLL, and can solve the problems of DAC with complex structure and large surface area

Inactive Publication Date: 2003-11-19
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the corresponding transistor circuit occupies a large amount of surface area on the integrated circuit and its wiring part will make the structure of the DAC quite complicated.

Method used

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  • Encoding up/down based D-A converter and delayed phase locking loop device and method therefor
  • Encoding up/down based D-A converter and delayed phase locking loop device and method therefor
  • Encoding up/down based D-A converter and delayed phase locking loop device and method therefor

Examples

Experimental program
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Embodiment Construction

[0059] Operation of a counter device according to an embodiment of the invention includes using a hybrid code representation having a non-N-based coin code portion and a non-N-based cash code portion A number based on N, said coin code corresponding to one or more of the least significant digits of said cash code but less than all of the bits of said cash code, said coin code portion of said mixed code representing a number based on N range, the range has an upper boundary and a lower boundary; if the trigger signal is used to increment the count (upcount), determine whether the previously obtained value of the coded part of the coin is equal to the upper boundary value; if it is determined that the previously obtained value of the coded part of the coin value is less than the upper boundary value, use the coin code part to count up; if it is determined that the previously obtained value of the coin code part is equal to the upper boundary value, use the cash code part to count...

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Abstract

A digital to analog converter (DAC) can comprise: an escalator code generator; and an escalator-code-to-analog converter (ECAC). The generator can (1) represent base 10 numbers with a mixed code having a coin code portion and a cash code portion, which will eliminate multi-bit changes in the cash code upon changes in count direction; and (2) represent a count in a first direction as the sum of the coin code and the cash code. The generator can alter the coin code when the count changes direction while the cash code remains the same until a count capacity of the coin code is exceeded, at which point the cash code can be altered. Cycling between adjacent base 10 numbers is absorbed by the coin code while keeping the cash code the same, which reduces noise introduced into an output of the ECAC due to such cycling.

Description

technical field [0001] The present invention relates to the fields of DAC (Digital / Analog Converter) and DLL (Delay Locked Loop), especially DAC and DLL based on escalator code. Background technique [0002] Newer integrated circuits attached to printed circuit boards (PCBs), such as Synchronous Dynamic Random Access Memory (SDRAM), RAMBUS DRAM, etc., include DLL (Delay Locked Loop) circuits. The DLL circuit maintains a predetermined phase relationship between an internal clock and an external reference or system clock, such as provided by a memory controller. [0003] In its simplest form, a DLL has a programmable delay line and some blocks of control logic. The delay line produces a delayed signal of the reference clock signal. The delayed clock signal is supplied to other internal circuits of the integrated circuit, such as a DRAM integrated circuit (IC), of which the DLL is a part. In addition to being supplied to other circuits of the IC, the internal clock signal is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/68G11C7/16G11C7/22H03L7/081H03L7/089H03M1/06H03M1/08H03M1/66H03M1/74H03M7/00
CPCH03M1/745H03L7/089G11C7/222H03M1/0863H03L7/0812G11C7/22G11C7/16H03M1/664H03M1/0687H03L7/0816H03M7/00
Inventor 郑人荣
Owner SAMSUNG ELECTRONICS CO LTD