Semiconductor storage device

Abstract

A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input / output of the charges to / from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor (32) with a storage node (30) located above a semiconductor substrate (1) and holding the charges corresponding to a logical level of stored binary information, an access transistor (T5, T6) located on the semiconductor substrate surface and controlling input / output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements (T1, T2, T3, T4, R1, R2) constituting the latch circuit is located above the access transistor.

Description

technical field [0001] The present invention relates to a semiconductor storage device, and more particularly to a DRAM (Dynamic Random-Access Memory: Dynamic Random-Access Memory) that does not require refreshing. technical background [0002] The structure of a conventional DRAM memory cell will be described below with reference to FIG. 11 . [0003] In this figure, an element isolation region 102 is provided on a silicon substrate 101 for isolating each element region. An n-type well 103 and a p-type well 104 are provided in the silicon substrate 101 on the lower side of the device region, and a gate oxide film 105 is provided next to the silicon substrate where the device is formed. Doped polysilicon 106 is provided on the gate oxide film 105, and a WSi layer 107 and a double-layer film 108 composed of a silicon oxide film and a silicon nitride film are disposed on the doped polysilicon 106. The gate electrode 109 includes the above-described doped polysilicon 106 , WS...

AI Technical Summary

Problems solved by technology

But in SRAM, each memory cell must form 6 transistors on the silicon substrate

So there is the problem that the memory cell is particularly large compared to DRAM

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