Semiconductor memory device

Abstract

A semiconductor memory device includes a replica circuit including a plurality of replica cells (RMC) having the same elements as those of memory cells in a memory array and outputting signals with levels in accordance with the stage number to a common replica bit line, and a sense amplifier control circuit for receiving a signal of the replica bit line to control a timing of a signal SAE for starting a sense amplifier circuit. The replica circuit includes a switching circuit (SW) for switching the stage number of the replica cells to be activated among the plurality of replica cells in a programmable manner.

Description

technical field [0001] The present invention relates to a semiconductor memory device which generates an activation timing signal of a sense amplifier circuit using a replica circuit including replica cells having the same structure as memory cells contained in a memory array. Background technique [0002] In conventional semiconductor memory devices, a method of generating a timing signal of a sense amplifier for amplifying read data from a memory cell to track the read timing of the memory cell to variations caused by processes and voltages is often employed. Among them, there is a method of programmably changing a timing signal using a replica circuit. This method will be described below. [0003] FIG. 11 is a functional block diagram showing an example of the structure of a conventional semiconductor memory device (see US Patent No. 6,172,925). In FIG. 11 , the existing semiconductor storage device has: a storage array of SRAM (hereinafter referred to as storage array)...

AI Technical Summary

Problems solved by technology

In addition, even for the selection line for selecting the duplication unit 909, the wiring area must be re-determined

The result is an increased layout area

Images