Parallel-serial multiplication-addition device
A technology of multiplier-adder and adder, applied in the field of parallel-serial multiplier-adder
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[0027] The framework of the present invention discloses a new LMS algorithm, and can be realized very effectively with the VLSI framework. The improved real number type LMS algorithm of the present invention can be represented by the following equation:
[0028] y ( n ) = Σ k = 0 N - 1 C k ( n - k ) x ( n - k )
[0029] e(n)=g(n)-y(n)
[0030] C k (n+1)=C k (n)+μe(n)x(n-k)
[0031] k=0, 1, . . . , N-1
[0032] Where x(n) is the filter input at time n; C k (n) is the kth filter coefficient at time n; y(n) is the filter output, g(n) is the expected result, e(n...
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