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Parallel-serial multiplication-addition device

A technology of multiplier-adder and adder, applied in the field of parallel-serial multiplier-adder

Inactive Publication Date: 2004-09-15
IND TECH RES INST
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0013] In order to overcome the inherent shortcomings of the standard LMS algorithm, several improvements have been proposed to solve the difficulties in hardware implementation, image 3 The prior art shown uses a direct transversal filter approach in the finite impulse response portion of the algorithm, but uses an updated and delayed version of the filter coefficients

Method used

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Embodiment Construction

[0027] The framework of the present invention discloses a new LMS algorithm, and can be realized very effectively with the VLSI framework. The improved real number type LMS algorithm of the present invention can be represented by the following equation:

[0028] y ( n ) = Σ k = 0 N - 1 C k ( n - k ) x ( n - k )

[0029] e(n)=g(n)-y(n)

[0030] C k (n+1)=C k (n)+μe(n)x(n-k)

[0031] k=0, 1, . . . , N-1

[0032] Where x(n) is the filter input at time n; C k (n) is the kth filter coefficient at time n; y(n) is the filter output, g(n) is the expected result, e(n...

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Abstract

The multiplying adder comprises a parallel-serial multiplier and a digital serial adder. The parallel-serial multiplier includes following components: a re-coder receives the multiplier, and outputs a ordered sequence re-coded; a partial product generator generates multiple partial products based on multiplicand and the said ordered sequence re-coded; a adder adds multiple partial products in order to synthesize the product. When partial products are carried out summation, the adder outputs least significant digit in intermediate sum of partial product in digital serial format. The digital serial adder includes a carry save adder for receiving product and input of accumulator in order to generate a output. The said output is a sum of the product of input of the accumulator.

Description

[0001] This application is a divisional application of an invention patent application with the application number 98104013.6 and the invention title "Pipelined Parallel-Serial Architecture Minimum Mean Square Adaptive Filter and Its Method". technical field [0002] The present invention relates to a multiplier-accumulator, in particular to a parallel-serial multiplier-accumulator for realizing the minimum mean square adaptive filter. Background technique [0003] The least mean square (Least Mean Spuare, hereinafter referred to as LMS) adaptive filter algorithm has many applications. In these LMS applications, where the statistical properties of the input process are unknown or change over time, such as noise cancellation, line enhancement, and adaptive array processing, the algorithm uses a transversal The filter (transversal filter) structure aims to minimize the mean square error (mean square error). [0004] The LMS algorithm is often chosen for hardware implementatio...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/15H03H21/00
CPCH03H21/0012
Inventor 钟和明黄国升苏文光徐朝辉
Owner IND TECH RES INST
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