Side wall spacing piece structure of self aligning contact and its shaping method

Abstract

Semiconductor devices such as DRAM cells include adjacent conductive patterns, for example bit lines or gate stacks, each comprising a conductive line and a capping layer on a semiconductor substrate. In order to reduce lateral erosion of sidewall spacers during etching to form contact holes, a first spacer layer is deposited between adjacent conductor lines, then a second spacer layer is deposited conformally over the conductor stacks and over first spacer layer. An interlayer insulating layer is formed on the conformal spacer layer, then the first spacer layer is etched using the second spacer layer as a mask, to form a single-layer spacer 85 which comprises two different dielectric materials, on the sidewalls of the conductive lines, concurrently with forming a contact hole.

Description

technical field [0001] The present invention relates to semiconductor devices, and more particularly to spacer structures for self-aligned contact (SAC) applications and methods of forming the same. technical background [0002] As semiconductor devices become more and more highly integrated, it becomes more and more difficult to ensure proper misalignment margins during the manufacturing process. This is partly due to limitations in lithography and etching techniques. For example, as the spacing between a node contact of a capacitor and its adjacent bitline decreases, it becomes increasingly difficult to form a contact hole between the bitlines without causing problems such as electrical shorts. [0003] Various attempts have been made in the industry to deal with these problems, such as using a self-aligned (SAC) process. 1A to 1E are cross-sectional views illustrating a process of forming a storage node contact using a conventional SAC process. Referring to FIG. 1A, a ...

AI Technical Summary

Problems solved by technology

In addition, since the single-layer spacer 180' may be over-etched during the formation of the contact hole 200, the thickness of the single-layer spacer 180' may become very thin.

This increases the bit line loading capacitance, preventing further integration of memory devices

[0006] Also, as part of the trend toward higher integration densities, contact hole heights are increasing while contact hole diameters are decreasing, causing an increase in aspect ratio (the ratio of height to width)

This makes it difficult to completely fill deep and narrow contact holes, resulting in voids in the intervening dielectric layer between wires (such as bit lines)

Such voids may grow during cleaning (eg, during a wet cleaning process), causing bridging between bit lines 150 and / or adjacent contact pads 130, which may cause short circuits.

[0007] There is therefore a need for an improved semiconductor fabrication process that can increase etch margin or shoulder width and potentially reduce bit line load capacitance while further reducing shoulder losses

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