Semiconductor storage device

Abstract

Provided is a means for determining whether the stress as prescribed is exerted or not at the disturbance test for a semiconductor storage device, at a low cost and without increasing the area of a chip. A memory cell array includes a memory cell area 11 consisting of memory cells MC<11>to MCand a sample cell area 12 consisting of word line sample cells SCW<11>to SCWand bit line sample cells SCB<11>to SCB<1n>, wherein the word line sample cells SCW<11>to SCWand the bit line sample cells SCB<11>to SCB<1n>are formed so that electric charges are easily movable from floating gate electrodes in accordance with voltages applied to word lines WL<1>to WLand bit lines BL<1>to BL, as compared with the memory cells MC<11>to MC.

Description

technical field [0001] The present invention relates to a semiconductor memory device having an electrically rewritable nonvolatile memory cell, and more particularly to a semiconductor memory device corresponding to an inspection method for inspecting nonvolatile memory cells using an aging process. Background technique [0002] Conventionally, as a semiconductor storage device that stores data in elements integrated on a semiconductor substrate, a nonvolatile semiconductor storage device capable of retaining data even when power supply is stopped has been used. In particular, electrically rewritable and electrically erasable flash memory EEPROM devices having a floating gate electrode whose periphery is insulated by an oxide film and a control gate electrode formed by interposing a capacitive insulating film on the floating gate electrode are widely used. [0003] (existing example 1) [0004] Figure 17 Shown is a block diagram of the configuration of the flash EEPROM de...

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Problems solved by technology

[0025] However, in the above-mentioned conventional example 2, in addition to the word line potential measurement circuit 112 and the bit line potential measurement circuit 113, a bit line selection transistor BST is provided. 1 ~BST n and the word line select transistor WSR 1 ~WST m Signal lines and control circuits controlled one by one, thus significantly increasing the chip area of ​​the flash EEPROM device 110

And in the burn-in device 200, in order to judge the potential of the word line and the potential of the bit line, it is also necessary to set the comparator 201 of the number of flash memory EEPROM devices that will be tested uniformly, and the required cost of the burn-in device has also increased.

[0026] Like this, in above-mentioned existing flash memory EEPROM device, if will certainly carry out interference test, just there is the problem of increasing the chip cost of flash memory EEPROM device and test expense

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