Semiconductor device and manufacturing method thereof
A semiconductor and device technology, applied in the field of channel region structure, can solve problems such as cycle extension and production cost increase
Inactive Publication Date: 2005-04-20
SEIKO INSTR INC
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Problems solved by technology
In addition, the cycle time for manufacturing semiconductor devices having different insulating films, different substrate concentrations or different conductivity type MOSFET threshold voltages is extended, and the production cost is also increased.
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[0158] Preferred embodiments of the present invention are described below with reference to the accompanying drawings.
[0159] figure 1 is a schematic plan view of the MOSFET according to the first embodiment of the present invention.
[0160]If the MOSFET of the first embodiment is an N-type MOSFET formed on a P-type semiconductor substrate, and the impurity concentration of the channel region 104 with the first impurity concentration is determined by the P-type semiconductor substrate, it has a second impurity concentration The impurity concentration of the channel region 105 is determined by the doping of impurities. The doping method is to optically form a pattern 106 with photoresist for the region selected as the doping of impurities, and to dope the impurities into the patterned area by ion implantation. The doped region used. The doped impurity forms a channel region with a second impurity concentration. Since the pattern 106 for doping is drawn in a direction para...
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A method of manufacturing a semiconductor device, comprising the steps of: forming a field insulating film on the surface of a first conductive type semiconductor region on a substrate surface; forming a field insulating film on the surface of the first and second transistor regions of the semiconductor region Photoresist, used to select the regions where gate insulating films with different thicknesses are formed; the gate insulating films with different thicknesses are formed corresponding to the shape of the photoresist; the channel impurity regions are formed on the surfaces of the first and second transistor regions; forming a gate electrode pattern on the gate insulating film; forming a source region and a drain region of the second conductive type on the surface of the first transistor region so that they are separated by a gate electrode; forming an interlayer insulating film on the gate electrode; forming a through A connection hole of the intermediate insulating film; and a metallized wiring pattern is formed and covered on the connection hole; the gate insulating film is divided, and between the source region and the drain region on the same channel, at least a plurality of plane-shaped ones have first and A gate insulating film region of a second thickness.
Description
[0001] This application is a divisional application of the original application with the application number 01122711.7 and the filing date on June 3, 1995. The first prior application of the original application is JP94-122872, and the first prior application date is June 3, 1994 day. technical field [0002] The present invention relates to a channel region structure of an insulated gate field effect transistor (hereinafter referred to as MOSFET) constituting a semiconductor device of an integrated circuit, and more particularly to a semiconductor device in which the impurity concentration and thickness of the gate insulating film determine The surface reverse voltage (threshold voltage) of the channel region is controlled. [0003] The present invention relates to a semiconductor device of an integrated circuit composed of MOSFETs having multiple threshold voltages on the same substrate, and a manufacturing method thereof. [0004] The present invention relates to a semicon...
Claims
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IPC IPC(8): H01L21/322H01L21/336H01L21/8234H01L27/07H01L29/10H01L29/786
CPCH01L21/3226H01L21/823462H01L27/0705H01L29/1041H01L29/1045H01L29/66757H01L29/78696
Inventor 宫城雅记小西春男久保和昭小岛芳和清水亭齐藤丰町田透金子哲也
Owner SEIKO INSTR INC