Semiconductor device and manufacturing method thereof
A semiconductor and device technology, applied in the field of channel region structure, can solve the problems of increased production cost and extended cycle
Inactive Publication Date: 2007-06-06
SEIKO INSTR INC
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- Description
- Claims
- Application Information
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Problems solved by technology
In addition, the cycle time for manufacturing semiconductor devices having different insulating films, different substrate concentrations or different conductivity type MOSFET threshold voltages is extended, and the production cost is also increased.
Method used
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Embodiment Construction
[0159] Preferred embodiments of the present invention are described below with reference to the accompanying drawings.
[0160] Fig. 1 is a schematic plan view of a MOSFET according to a first embodiment of the present invention.
[0161]If the MOSFET of the first embodiment is an N-type MOSFET formed on a P-type semiconductor substrate, and the impurity concentration of the channel region 104 with the first impurity concentration is determined by the P-type semiconductor substrate, it has a second impurity concentration The impurity concentration of the channel region 105 is determined by the doping of impurities. The doping method is to optically form a pattern 106 with photoresist for the region selected as the doping of impurities, and to dope the impurities into the patterned area by ion implantation. The doped region used. The doped impurity forms a channel region with a second impurity concentration. Since the pattern 106 for doping is drawn in a direction parallel to ...
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The invention relates to a method for producing semiconductor which is characterized in that the invention comprises the following steps: the first conduction semiconductor surface forms a dielectric film; the surface of the first and the second transistor area of the semiconductor area forms a photosensitive resist for choosing the area of the dielectric film forming different thickness; the gate dielectric film with different thickness is formed corresponding to the shape of the photosensitive resist; a groove impurity area is formed at the surface of the first and second transistor areas; a gate electrode figure is formed at a gate dielectric film; a second conduction source region and drain region is formed at the surface of the first transistor area thereby being separated by a gate electrode; a mesosphere dielectric film is formed at the gate electrode; a connecting hole through the mesosphere dielectric film is formed; a metal wiring pattern is formed and covered at the connecting hole; the cutting gate dielectric film forms the gate dielectric film area with the first and the second thickness of the plane between the source area and the drain area at the same groove.
Description
[0001] This application is a divisional application of the original application with the application number 01122711.7 and the filing date on June 3, 1995. The first prior application of the original application is JP94-122872, and the first prior application date is June 3, 1994 day. technical field [0002] The present invention relates to a channel region structure of an insulated gate field effect transistor (hereinafter referred to as MOSFET) constituting a semiconductor device of an integrated circuit, and more particularly to a semiconductor device in which the impurity concentration and thickness of the gate insulating film determine The surface reverse voltage (threshold voltage) of the channel region is controlled. [0003] The present invention relates to a semiconductor device of an integrated circuit composed of MOSFETs having multiple threshold voltages on the same substrate, and a manufacturing method thereof. [0004] The present invention relates to a semicon...
Claims
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IPC IPC(8): H01L21/336H01L21/8234H01L21/28H01L21/322H01L27/07H01L29/10H01L29/786
CPCH01L21/3226H01L29/1045H01L27/0705H01L29/66757H01L29/78696H01L21/823462H01L29/1041
Inventor 宫城雅记小西春男久保和昭小岛芳和清水亭齐藤丰町田透金子哲也
Owner SEIKO INSTR INC