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Novel finishing pad design for multidirectional use

A multi-faceted, polishing pad technology, applied in the field of planarization, can solve the problems of increasing the overall cost, delay, damage to the wafer, etc., to achieve the effect of accelerating integrated circuit manufacturing, reducing related costs and

Inactive Publication Date: 2005-09-07
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The transfer and cleaning of wafers cause delays in the integrated circuit manufacturing process and increase the overall cost. In addition, the movement of wafers into and out of the station increases the probability of damage to wafers

Method used

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  • Novel finishing pad design for multidirectional use
  • Novel finishing pad design for multidirectional use
  • Novel finishing pad design for multidirectional use

Examples

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Embodiment Construction

[0018] The making and using of various specific embodiments are described in detail below, however, it should be appreciated that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

[0019] Referring to Figures 1a and 1b, there are illustrated top views of a prior art disc-based semiconductor wafer planarizer and polisher and detailed views of prior art embodiments of polishing disc surfaces. Using a polishing pad is one way of planarizing a semiconductor wafer. The planarization of the semiconductor wafer includes planarizing the semiconductor wafer and then polishing at least one of the two surfaces of the semiconductor wafer to a mirror-like finish.

[0020] A polishing plate, such as polishing plate 105 , is rotated in a clockwise or counterclockwis...

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PUM

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Abstract

A polishing pad (for example, polishing pad 305) for use in planarization of a semiconductor wafer (for example, semiconductor wafer 420), the polishing pad 305 featuring a plurality of different polishing surfaces, depending upon the direction of the movement of the polishing pad 305. The polishing pad 305 may take the from of a polishing disc or a polishing belt. The planarization of the semiconductor wafer 420 can then take place at a fewer number of polishing stations, thereby reducing the amount of time needed and reducing the probability of damage to the semiconductor wafer 420.

Description

technical field [0001] The present invention relates generally to integrated circuit fabrication and in particular to the preparation of the surface of semiconductor wafers, commonly referred to as planarization, prior to actual integrated circuit fabrication. technical background [0002] Before and during the actual integrated circuit production process, the semiconductor wafers (or simply called wafers) used for integrated circuit fabrication must be manufactured substantially flat and smooth, and the wafer must be completely flat and smooth to increase wafer density. Round yield, that is, maximizing the number of good integrated circuits produced on a wafer. Wafers that are not flat or have grooves, notches, or scratches are likely to produce a significant number of defective integrated circuits if the wafer is to be used non-planarized to produce integrated circuits. [0003] Wafers are typically taken from large ingots of semiconductor material and then planarized and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): B24B57/02B24B21/00B24B37/24B24D13/14H01L21/304
CPCB24B37/24
Inventor M·瑙科克
Owner INFINEON TECH AG