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Evaluation chip

一种芯片、优先级的技术，应用在仪器、电数字数据处理、检测有故障的计算机硬件等方向，能够解决不能使用EVA芯片等问题，达到增加便利性、防止空间不足、降低成本的效果

Inactive Publication Date: 2005-09-28
OKI ELECTRIC IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the disadvantage and inconvenience of the EVA chip including the conventional interrupt circuit is that when the priority order specification in the interrupt section of the internal CPU section changes, or the priority order specification of the interrupt section in the CPU section of a series of products changes. At the same time, since the interrupt priority as a feature of the EVA chip is fixed, the EVA chip cannot be used

Method used

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Embodiment 1

[0020] structure

[0021] figure 1 is a schematic diagram of the EVA chip 10 according to the first embodiment (Embodiment 1) of the present invention.

[0022] The EVA chip 10 evaluates programs stored in the external program memory 100 . The EVA chip 10 includes: four groups of control signal input terminals 11-1 to 11-4, 12-1 to 12-4, 13-1 to 13-4, and 14-1 to 14-4; four interrupt request signal input terminals terminals 15 - 1 to 15 - 4 ; a command input terminal 16 ; an address output terminal 17 ; a plurality of data output terminals 18 ; and a plurality of control signal output terminals 19 . A plurality of (for example, four) four-bit control signals S11, S12, S13, and S14 for modifying and controlling the order of interrupt priority of the program are input to the four sets of control signal input terminals 11-1 to 11-4, 12, respectively. -1 to 12-4, 13-1 to 13-4, and 14-1 to 14-4. Four interrupt request signals are input to the four interrupt request signal inp...

Embodiment 2

[0045] structure

[0046] figure 2 is a schematic diagram showing an EVA chip 10A according to a second embodiment (Embodiment 2) of the present invention. and figure 1 Similar symbols are used for the same or similar structural elements in Embodiment 1.

[0047] In the EVA chip 10 of Embodiment 1, control signal input terminals 11-1 to 11-4, 12-1 to 12-4, 13-1 to 13-4, and 14-1 to 14-4 are provided to The interrupt priority order of the interrupt modules 30-1 to 30-4 is switched. The difference is that in the EVA chip 10A of Embodiment 2, four data input terminals 61 to 64, and four priority order control registers 71 to 74 respectively connected to these terminals are provided instead of the control signal input terminals 11- 1 to 11-4, 12-1 to 12-4, 13-1 to 13-4, and 14-1 to 14-4.

[0048] Data on the priority order of interrupts is input to the data input terminals 61 to 64 from the CPU controlling the EVA chip 10A. The priority order control registers 71 to 74 ar...

Embodiment 3

[0061] structure

[0062] image 3 is a schematic diagram of an EVA chip 10B according to a third embodiment (Embodiment 3) of the present invention. and figure 1 Example 1 in and figure 2 Similar reference numerals are used for the same structural elements in Embodiment 2.

[0063] In the EVA chip 10A of Embodiment 2, data input terminals 61 to 64 and priority order control registers 71 to 74 are provided to switch the interrupt priority order of the interrupt modules 30-1 to 30-4. The difference is that in the EVA chip 10B of Embodiment 3, three input terminals 81 to 83 and a 12-bit interrupt priority sequence control shift register 90 connected to these terminals are provided instead of the data input terminals 61 to 64 and Priority order control registers 71 to 74.

[0064] At the input terminal 81, the serial 12-bit priority order data S81 is input from the outside, at the input terminal 82, the synchronous clock S82 is input from the outside; and at the input ter...

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Abstract

An evaluation chip is disclosed whose interrupt priority order can be changed freely. A plurality of interrupt priority order determining circuits 20 - 1 to 2 - 4 perform a logical operation on a plurality of signals S 11 to S 14 used for interrupt priority order modifying control that are applied from outside and a plurality of interrupt signals S 31 - 1 to S 31 - 4 , and output interrupt modifying signals S 24 - 1 to S 24 - 4 . A plurality of interrupt modules 30 - 1 to 30 - 4 perform a logical AND operation on the plurality of signals S 24 - 1 to S 24 - 4 and a plurality of interrupt request signals S 15 - 1 to S 15 - 4 that are applied from outside, and output the signals S 31 - 1 to S 31 - 4 . An address generating circuit 40 encodes the plurality of signals S 31 - 1 to S 31 - 4 and generates interrupt vector addresses 40 . A microcomputer core 50 executes interrupt instructions that have been fetched from an external program memory 100 , based on the addresses S 40.

Description

technical field [0001] The present invention relates to an evaluation chip (hereinafter referred to as "EVA chip") such as an integrated circuit for program development of a microcomputer used in an emulator. The invention specifically relates to an EVA chip which can change the interrupt priority order of instruction execution at will. Background technique [0002] For example, a conventional EVA chip is disclosed in JP H5-151014A. JPH5-151014A discloses an EVA chip that evaluates a program stored in an external program memory and includes, for example, a central processing unit (hereinafter referred to as "CPU") section and a data latch section. In this EVA chip, the instruction read from the program memory is decoded, and the decoded result is executed by the CPU part. After instruction execution results are temporarily held in the data latch section, these results are selectively output to the outside of the chip. These data are evaluated, for example, by an externall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/36G06F13/26
CPCG06F13/26
Inventor 山崎博长友宪一郎
Owner OKI ELECTRIC IND CO LTD
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