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Semiconductor protection device

一种保护装置、半导体的技术，应用在半导体器件、半导体/固态器件零部件、晶体管等方向，能够解决增大、芯片规模和成本增大、大芯片规模和成本等问题

Inactive Publication Date: 2005-12-28
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, for products in which the high-potential power supply (VDD) and low-potential power supply (VSS) power pads are separated by a few millimeters, wiring resistor widths of hundreds of microns are required
This wider wiring resistance width leads to larger chip size and cost increase, so the existing technology needs further improvement
Another way to solve the above problems is to add a power diode, however, this method also leads to a larger chip size and increased cost, so the existing technology still needs further improvement

Method used

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  • Semiconductor protection device
  • Semiconductor protection device
  • Semiconductor protection device

Examples

Experimental program
Comparison scheme
Effect test

no. 2 example

[0040] figure 2 is a cross-sectional view of the PNP bipolar transistor 120 of this embodiment. This circuit diagram is the same as that used for the first embodiment Figure 1B Same as shown.

[0041] In this embodiment, the N-type diffusion layer 115 is formed so that only the P + The bottom portion of the diffusion layer 114b surrounds P + Diffusion layer 114b.

[0042] In this example, only at P + The bottom portion of the diffusion layer 114b surrounds P + diffusion layer 114b, so the process is mainly related to P + Diffusion layer 114a and P + The doping (impurity) concentration profile is the same between the diffusion layers 114b. As a result, the operability of the PNP bipolar transistor 20 can be maintained, and the protection of the internal circuit 121 from static electricity applied from, for example, the power supply terminal of the high-potential power supply 102 can be improved. Therefore, the PNP bipolar transistor 120 can effectively protect the in...

no. 3 example

[0044] image 3 is a cross-sectional view of the PNP bipolar transistor 120 of this embodiment. In this embodiment, a P connected to the low potential power supply (VSS) 103 is formed. + Diffusion layer 116 so as to intersect the outermost peripheral surface of P-type well 140 and the outermost peripheral surface of N-type well 113 of PNP bipolar transistor 120 . In this embodiment, an N-type diffusion layer 115 will also be formed to surround the P + Diffusion layer 116 .

[0045] The P + The diffusion layer 116 includes a parasitic diode 125 and an N-type well 113 connected to a high potential power supply (VDD) 102 . This parasitic diode 125 further facilitates protection of Figure 1B The protection of the internal circuit is shown from being damaged by static electricity applied from the power supply terminal of the high-potential power supply (VDD) 102 . Therefore, the PNP bipolar transistor 120 can effectively protect the internal circuit.

[0046] In this embodi...

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Abstract

A semiconductor protection device for effectively protecting internal circuits in a semiconductor integrated circuit, wherein an N-type diffusion layer is formed so as to surround a P+ doped diffusion layer. Due to the formation of the N-type diffusion layer, the N-type impurity concentration around the parasitic diode increases, thereby setting the breakdown voltage of the parasitic diode connected to the collector to be lower than that of the parasitic diode connected to the emitter. In other words, the diode breakdown voltage is determined according to whether the impurity concentration at the periphery of the available diode is high or low, and the higher the impurity concentration, the lower the breakdown voltage. Therefore, clamping of the parasitic diode connected between the high-potential power supply and the low-potential power supply is facilitated so that current can easily flow in the opposite direction so that internal circuits can be prevented from being damaged by static electricity applied from the power supply terminal.

Description

technical field [0001] The present invention relates to a protection device, and more particularly, to a semiconductor protection circuit for protecting a semiconductor integrated circuit (LSI) from damage due to static electricity or the like. Background technique [0002] In the prior art, a protection circuit is formed near an LSI chip for preventing damage to internal elements of the LSI due to static electricity applied from external components. Fig. 6 is a diagram showing an example of a related art protection device. Figure 6A is a circuit diagram of the prior art. Figure 6B with 6C is a plan view of a prior art PNP bipolar transistor 120 . Figure 6D is along Figure 6C with Figure 6B The cross-sectional view obtained by the line A-A' shown. for such as Figure 6A The protection circuit for the I / O pad 1 of the shown example is formed by a PNP bipolar transistor 20 . The emitter (E) of the PNP bipolar transistor 20 is connected to the I / O pad 1, the base (B)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/60H01L27/02H01L29/18H01L29/74
CPCH01L27/0255H01L27/0259H01L29/7436
Inventor 高桥幸雄
Owner RENESAS ELECTRONICS CORP