Equiphase multi-phase clock signal generator circuit and serial digital data receiving circuit using the same
A technology of signal generating circuit and clock signal, which is applied in the direction of electrical components, automatic power control, pulse processing, etc., can solve the problems of circuit scale enlargement, increase of semiconductor substrate circuit area and power consumption, etc., and achieve reduction of circuit area , Reduce operating noise and reduce power consumption
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[0082] refer to Figure 6 , to illustrate the serial digital data receiving circuit using the equal-phase multi-phase clock signal generating circuit of the present invention in this embodiment.
[0083] 600 is a serial digital data receiving circuit, which has two buffers 601 , a parallelization circuit (De-Serializer) 604 , a multiplexer (Multiplexer) circuit 605 and an equal-phase multi-phase clock signal generation circuit 100 . A reference clock 701 and serial digital data 702 are input to the serial digital data receiving circuit 600 from outside the circuit.
[0084] Furthermore, the equiphase multiphase clock signal generation circuit 100 can use the circuits described in the above-mentioned embodiments. and, in Figure 6 In , the multiple phase comparison circuit is marked as "PD", the loop filter is marked as "LPF", and the complementary voltage control delay element column is marked as "VCD".
[0085] In the serial digital data receiving circuit 600 , serial digi...
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