On-chip data transmission control apparatus and method

Abstract

The on-chip data transmission controller comprises a data comparison unit for comparing current data with previous data and issuing an inversion flag if the number of data bits phase-transited is larger than a preset number, a first data inversion unit for inverting a phase of the current data when the inversion flag is activated and providing inverted data onto a data bus, and a second data inversion unit for inverting a phase of the data transmitted via the data bus when the inversion flag is activated and outputting inverted data. Through this controller, an on-chip noise that largely occurs as the number of data to be transmitted increases can be reduced, by decreasing transition number of data inputted via the GIO line, in case of using a multi step pre-patch structure to improve an operation speed of a memory device.

Description

technical field [0001] The present invention relates to on-chip data transmission; and more particularly, to an on-chip data transmission control device and method capable of improving the operating characteristics of chip devices by suppressing the occurrence of on-chip noise. If after sensing a number of phase shifted data bits in the data output via the data bus, the rate at which the data is transitioned ("transition rate") is higher than a preset rate, this is done by inverting the data to be transmitted and reducing the The conversion ratio was achieved. Background technique [0002] FIG. 1 is a circuit diagram showing the configuration of a conventional on-chip data output device. [0003] In particular, FIG. 1 depicts the configuration of a conventional on-chip data output device using an external input / output (I / O) and 4-bit pre-patch. In this structure, the number of I / Os basically necessary for communication with the outside is 1 and the operation speed of the m...

AI Technical Summary

Problems solved by technology

This causes on-chip noise and in turn leads to failure of the chip

Images