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Instruction for initiation of concurrent instruction streams in a multithreading microprocessor

A microprocessor and instruction technology, applied in the field of new thread instructions, can solve problems such as short execution time

Inactive Publication Date: 2006-10-04
MIPS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, certain applications may benefit from relatively frequently created threads with relatively short execution times, in which case the thread creation overhead must be short enough to achieve reasonably high performance from multithreading

Method used

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  • Instruction for initiation of concurrent instruction streams in a multithreading microprocessor
  • Instruction for initiation of concurrent instruction streams in a multithreading microprocessor
  • Instruction for initiation of concurrent instruction streams in a multithreading microprocessor

Examples

Experimental program
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Embodiment Construction

[0026] see now figure 1 , shows a block diagram of a computer system 100 according to the present invention. The computer system 100 includes a multithreaded processor 102 coupled to a system interface controller 104 . The system interface controller 104 is coupled to a system memory 108 and a plurality of input / output (I / O) devices 106 . Each input / output (I / O) device 106 provides an interrupt request line 112 to the microprocessor 102 . The computer system 100 may be, but not limited to, a general-purpose programmable computer system, a server computer, a workstation computer, a personal computer, a notebook computer, a personal digital assistant (PDA) or an embedded system (Embedded system). Examples are, but are not limited to, network routers or switches, printers, mass storage controllers, cameras, scanners, automotive control systems, and more.

[0027] The system memory 108 includes memory, such as random access memory (RAM) or read-only memory, for storing program ...

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PUM

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Abstract

A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and a second operand. The microprocessor executes the fork instruction by allocating context for the new thread, copying the first operand to a program counter of the new thread context, copying the second operand to a register of the new thread context, and scheduling the new thread for execution. If no new thread context is free for allocation, the microprocessor raises an exception to the fork instruction. The fork instruction is efficient because it does not copy the parent thread general purpose registers to the new thread. The second operand is typically used as a pointer to a data structure in memory containing initial general purpose register set values for the new thread.

Description

[0001] Related Application Cross Reference [0002] Application number (docket number) Date of Application topic 10 / 684350 (MIPS.0188-01-US) 10 / 10 / 03 Used to ensure execution on a multi-threaded processor QoS mechanism of the program (MECHANISMS FOR ASSURIG QUALITY OF SERVICE FOR PROGRAMS EXECUTING ON A MULTITHRE RADED PROCESSOR) 10 / 684348 (MIPS.0189-00-US) 10 / 10 / 03 Used to suspend and release execution in one processor The integration mechanism of computing threads (INTEGRATED MECHANISM FOR SUSPENSION AND DEALLOCATION OF COMPUTATIONAL THREADS OF EXECUTION IN A PROCESSOR) [0003] Application number (docket number) Date of Application topic 60 / 499180 (MIPS.0188-00-US) 8 / 28 / 03 Multithreaded Application Specific Extensions (MULTITHREADI...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46
Inventor 凯文·基塞尔
Owner MIPS TECH INC