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Error detection and correction method and apparatus in a magnetoresistive random access memory

A magnetoresistive random access, error correction code technology, applied in error detection/correction, digital signal error detection/correction, redundancy code for error detection, etc., can solve problems affecting data integrity and so on

Inactive Publication Date: 2006-11-15
INFINEON TECH AG +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0011] In addition to these challenges affecting data integrity, there are many other issues that can adversely affect data, including operating conditions such as temperature and charge

Method used

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  • Error detection and correction method and apparatus in a magnetoresistive random access memory
  • Error detection and correction method and apparatus in a magnetoresistive random access memory
  • Error detection and correction method and apparatus in a magnetoresistive random access memory

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Embodiment Construction

[0020] The first embodiment of the present invention relies on the use of error correction code (ECC) for checking and correcting errors in data stored in the MRAM to allow for a reduction in the switching current of the MRAM. There are many advantages gained from reducing the switch current, as will be described more fully below. Additionally, according to another embodiment of the present invention, error detection and correction is combined with refresh cycles to achieve greater benefits than would be possible with ECC alone or refresh cycles alone.

[0021] exist figure 2 A system block diagram according to one embodiment of the present invention is illustrated in . In this embodiment, an input output (I / O) interface (210) receives data to be processed (240). I / O interface (210) is in electronic communication with ECC processor (220), which generates ECC check bits for data bits received from I / O interface (210). The data bits and associated ECC check bits are then stor...

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Abstract

The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Description

technical field [0001] The present invention relates to a method and apparatus for reducing data errors generated in a magnetoresistive random access memory (MRAM), and more particularly, to a method of reducing switching current in order to protect data integrity in the MRAM. Background technique [0002] Recent developments have combined semiconductor technology with magnetic principles to create magnetoresistive random access memory (MRAM) devices. In this method, charge generation indicating the presence of a binary "1" or "0" is replaced by electron spins obtained by using a magnetic layer. [0003] MRAM includes a large number of conductive lines arranged perpendicular to each other in different metal layers. The points where vertical conductive lines cross are called intersection points. At each intersection, a magnetic stack is placed between two perpendicular conductive lines. [0004] Binary information represented as "0" or "1" is stored as different arrangemen...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/00G06F11/10G11C7/24G11C11/15G11C11/406
CPCG06F11/106G11C7/24G11C11/406G11B20/18G11B20/10
Inventor J·德布罗泽H·赫尼施密德R·勒伊施纳G·米勒
Owner INFINEON TECH AG
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