Memory control system and memory control circuit

Abstract

A memory control system includes a first memory for accessing a CPU via an address bus and a data bus, an SDRAM for accessing a CPU via the address bus and the data bus, a SDRAM control circuit for outputting a refresh request to the DRAM and a selection unit for selecting a signal line of the address bus and outputting a signal of the signal line corresponding to the refresh request of the SDRAM control circuit to the SDRAM.

Description

technical field [0001] The invention relates to a memory control system and a memory control circuit, in particular to a memory control circuit with multiple external memories. Background technique [0002] Systems with external memory such as SDRAM (Synchronous Dynamic Random Access Memory) and flash memory or SDRAM and SRAM (Static Random Access Memory) are known. Usually in such systems, a memory bus is shared among these external memories. [0003] Among DRAM devices, SDRAM devices are different from EDO (Extended Data Out) DRAM devices. In the SDRAM device, various commands can be input by combining control signals such as / RAS (Row Address Strobe) signal, / CAS (Column Address Strobe) signal, / WE (Write Enable) signal and the like. [0004] An SDRAM device usually has multiple memory banks. In SDRAM, each memory bank is independently accessible. In such an SDRAM device, when a refresh operation is performed, all banks must be precharged and the SDRAM device must be ...

AI Technical Summary

Problems solved by technology

However, Japanese Unexamined Patent Application Publication No. 11-7763 only discloses the conventional DRAM technology and does not disclose the refresh operation of SDRAM

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